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total search18 articles
2006-10-19 IC firms collaborate with Synopsys to validate new ATPG tech
Synopsys has collaborated with several semiconductor firms to test a new ATPG technology designed to increase the quality of manufacturing tests by targeting small delay defects
2002-12-02 Assertion-based approach saves time
Functional verification may determine which companies will dominate and design-for-verification and ABV improve the efficiency and effectiveness of functional verification.
2013-01-24 Imec, Cadence team up for DFT solution for 3D memory
Cadence's and imec's solution includes generation of DRAM test control signals in the logic die and inclusion of the DRAM boundary scan registers test access mechanisms of the 3D test architecture.
2003-02-03 The battle over BIST
Design-for-test is extremely competitive and that BIST has become the place to be; designers will need to sort through differing claims as the battle of BIST heats up.
2006-12-18 Test tool optimizes data for IC yield
LogicVision Inc. touts its solution Yield Insight to provide "yield learning," a process in which test failure data can pinpoint potential yield problems.
2000-12-01 SoCs likely to pose heading-off test problems
This technology news article describes the problems and solutions test engineers should face when confronting SoC designs.
2005-01-17 Good bridge testing needed
Combating bridging defects becomes prevalent as chip design processes continue to shrink from 90nm below.
2013-01-31 EDA tools stunted due to lack of complaints, says Nvidia exec
Jonah Alben, an executive at Nvidia, stated that cultural complacency and "uncomplaining" engineers are the primary culprits for the stunted growth of EDA tool investment.
2015-02-11 Detect physical defects using advanced fault models
Here is a look at the use of advanced fault model for detection of physical defects that cannot be detected using conventional Single Stuck-at and Transition Fault models.
2011-10-14 Reduce yield fallout by avoiding over and under at-speed testing
Here's a look at the problems associated with SoC at-speed testing such as overtesting and under-testing. This article also provides suggestions on how to overcome them.
2006-06-16 Low-power IC test can be trying
For designers, power management means controlling leakage power lost during standby mode and dynamic power consumption when multiple transistors switch in unison to perform desired functions.
2013-04-15 How to recover lost yield
A systematic optimisation methodology may be used to shape the design's digital power noise signature, and counteract both dynamic voltage drop and on-chip noise to recover the lost yield.
2015-02-09 Hardware emulation: The most versatile of them all
Nowadays, one of the most popular verification tools is hardware emulation and it might remain so in the next few years. Here is a look at the reasons behind its eminent success.
2001-03-01 Embedded test complicates SoC realm
SoC devices today implement a variety of specialized microelectronic functions. Those functions, sometimes with embedded systems, typically comprise of hardware or software design objects.
2007-08-16 Create high-quality program for at-speed test
At-speed test has been improved by a number of new capabilities, including the use of on-chip-generated functional clocks during test mode. This article offers some do's and don'ts for creating a high-quality program for at-speed test.
2004-10-27 Cadence claims industry's first 'yield diagnostics'
Claiming to offer the industry's first yield diagnostics tools, Cadence Design Systems introduced last week Encounter Diagnostics.
2012-02-03 Advances in 3D-IC testing
Read about the design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute based on the Synopsys test solution.
2011-10-12 A practical way of inspecting IP quality
Find out how to set up a process which can give you solid incoming IP quality inspectiona process that quite likely finds potential problems you may not have checked before, all with a minimum of overhead both in maintenance and in cycle time.
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