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2005-06-20 Photron, AccelChip apply digital filter design into FPGAs for wireless tech
Photron Technologies Ltd and AccelChip Inc. have redefined the next-generation of wireless communications with the FPGA implementation of a patented digital filter that will be a vital part for wireless data transmission rates of 100bps/Hz.
2002-04-04 AccelChip tool synthesizes Matlab designs
AccelChip Inc. believes it has cracked a longstanding design problem with a new tool that creates synthesizable Verilog and VHDL code from Matlab and Simulink designs for use in Xilinx or Altera FPGAs.
2004-06-08 AccelChip partners with Leopard Logic, ChipX
EDA startup AccelChip Inc., a provider of tools for synthesizable Verilog and VHDL code, has signed separate partnership deals with structured ASIC vendor ChipX and configurable logic vendor Leopard Logic.
2005-07-29 AccelChip offering cores through Xilinx program
Claiming to be the industry's first to do so, AccelChip Inc. said Wednesday (July 27) it has begun providing a family of fixed-point linear algebra intellectual property (IP) cores for Xilinx field-programmable gate array (FPGA) devices.
2004-09-30 AccelChip links to CoWare, Mentor tools
AccelChip Inc. said it has teamed with SystemC tool vendor CoWare Inc. and, separately, with Mentor Graphics to provide advanced design and verification flows for DSP design.
2003-10-30 AccelChip acquires DSP model vendor
DSP synthesis tool vendor AccelChip has acquired tiny DSP model developer Bit-tru Inc. for an undisclosed amount.
2006-01-17 Xilinx acquires MATLAB provider
Xilinx announced that it has acquired AccelChip, one of the leading providers of MATLAB synthesis software tools for building digital signal processing systems.
2005-06-08 SVD core generator speeds work on sensor array algorithms
Aimed at sensor array processing, AccelChip's new SVD core generator should cut development time for algorithms that contain SVD matrix inversion and factorization
2005-08-10 Revised model-based DSP tools pitch higher performance
The 2005.3 versions of AccelChip DSP synthesis tool and related intellectual property core generators for MATLAB model-based design of DSP products promise higher performance circuits and higher speed
2005-08-30 Revised model-based DSP tools pitch higher performance
The 2005.3 versions of AccelChip DSP synthesis tool and related IP core generators for MATLAB model-based design of DSP products promise higher performance circuits, higher speed, and streaming I/O microarchitectures for FFTs
2005-04-18 New IP line offers first RTL cores for linear algebra
The new AccelCore line from AccelChip offers algorithm developers and hardware engineers the industry's first fixed-point linear algebra IP as standalone resistor-transistor logic (RTL) cores.
2003-05-09 FPGA tools startup raises $6.6 million
Boosting its ability to bring its FPGA synthesis tools into the marketplace, AccelChip Inc. has announced the closing of a second round of venture funding for $6.6 million.
2006-04-07 Xilinx beefs up AccelDSP Synthesis tool
Xilinx announced the immediate availability of the new AccelDSP Synthesis 8.1 tool and AccelWare DSP libraries of algorithmic intellectual property.
2011-02-02 Xilinx acquires EDA vendor AutoESL
Xilinx has acquired high-level synthesis vendor AutoESL in hopes of serving more companies whose system architects and hardware designers work at a higher level of abstraction in C, C++ and System C.
2004-12-23 Xiliinx launches $100 million 'Ecosystem Venture Fund
With a brief to promote system-level design using FPGAs and other programmable platforms FPGA vendor Xilinx Inc. has launched a $100 million venture capital fund.
2006-11-01 HDL Coder offers shortcut to IC design
The Mathworks Inc. offers the Simulink HDL Coder, which automatically generates synthesizable Verilog and VHDL from Simulink models and Stateflow diagrams.
2004-06-01 EDA startup preps tools for RTL closure
Blue Pearl Software said its upcoming technology will identify and fix functional and DFT errors in RTL code, locate false paths and automatically generate timing constraints for synthesis.
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