Stay in touch with EE Times Asia

EE Times-Asia > Advanced Search > accellera

accellera Search results

Article
(115)
Forum
(0)
Blog
(0)

total search115 articles

2006-09-21	Synopsys donates power management tech to Accellera Synopsys has donated power management technology to Accellera, the EDA organization focused on electronic design automation standards.
2007-07-30	Nokia, ARM among companies in Accellera board EDA standards organization Accellera has elected 14 Corporate-Member companies to its Board of Directors for the 2007-2008 membership year, among which are Nokia and ARM.
2004-05-19	EDA vendor, Accellera moves place SystemVerilog at crossroads Two new developments raise questions about whether the emerging SystemVerilog language is heading for greater harmony or further acrimony.
2002-05-03	Cadence supports Accellera specification language Cadence Design Systems Inc. has revealed that it is supporting the standard property specification language defined by Accellera to enable assertion-based simulation and formal verification.
2005-03-28	Cadence contribution to Accellera standardize IC design kits Cadence Design Systems Inc. has contributed its custom-design schematic symbol set to the OpenKit Initiative.
2011-06-23	Accellera, OSCI team up unifies EDA standards Accellera and OSCI are joining forces to create a single organization, a move that will accelerate development of system-level standards as well as chip design and verification standards.
2003-10-13	Accellera, IEEE approve revised design standards Accellera and the IEEE Standards Association (IEEE-SA) announced that Accellera's Advanced Library Format has been approved as IEEE 1603-2003.
2014-06-05	Accellera updates Verilog-AMS with verification, modelling The enhanced features of Verilog-AMS 2.4 include supply sensitive connect modules, an analogue event type to enable efficient electrical-to-real conversion and current checker modules.
2007-02-01	Accellera to define verification coverage metrics Responding to user calls for a consistent way to measure functional-verification completeness, the Accellera standards organization has launched the Unified Coverage Interoperability to define standards that enable the sharing and analysis of coverage data by different tools during the verification process.
2002-01-14	Accellera standards group creates designers forum EDA standards organization Accellera has launched a forum to let design tool users identify, participate in and drive future industry standards.
2011-02-01	Accellera releases new EDA modeling standard The standards organization announced the approval of a new version of the Co-Emulation Modeling Interface (SCE-MI) specification as a new verification standard.
2011-05-02	Accellera leads IP tagging standard creation According to Accellera, an IP tagging standard would help track IP information as it passes through each level of the development process, and more importantly, as it reaches the final GDSII database.
2003-06-10	Accellera launches new verification standards Accellera announced that its Board and Technical Committee members have approved four new standards for language-based design verification.
2013-04-04	Accellera launches EDA, IP interoperability standardisation The company formed a multi-language working group to create a standard and functional reference for interoperability of multi-language verification environments and components.
2005-08-29	Accellera approves open verification library standard Open Verification Library (OVL) 1.0 has been approved by EDA standards organization Accellera's board of directors
2006-07-26	Accellera approves new VHDL standard Accellera announced that its members approved a new VHDL standard, a VHDL Applications Programming Interface (API) known as VHPI on June 28.
2004-04-15	Accellera advances SystemVerilog, joins IEEE-SA Taking SystemVerilog to the next step, Accellera's technical committee has unanimously approved the SystemVerilog 3.1a standard, slated for transfer to the IEEE in June 2004.
2004-06-08	0-In tools support Accellera SystemVerilog 3.1a 0-In Design Automation announced products within its Archer Verification system that provide support for Accellera's SystemVerilog 3.1a design constructs and IEEE-1076 VHDL.
2003-09-09	Verilog won't diverge, user reps pledge Although the IEEE and the Accellera standards organization appear to be heading in different directions with next-gen Verilog, IEEE 1364 Working Group and Accellera's SystemVerilog committee members said they won't allow incompatible standards to emerge.
2003-06-05	TransEDA debuts property verification tool TransEDA has announced a property and assertion capture and validation tool at the 2003 Design Automation Conference.
2004-01-08	Transaction-level emulation platform rolls out Emulation and Verification Engineering SA and Zaiq Technologies Inc. are teaming up to announce a transaction-level verification platform.
2007-02-21	SystemVerilog falls short for design SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support.
2004-02-02	Synopsys, Cadence give nod to SystemVerilog changes Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2002-09-18	Sugar language sweetens assertions Three EDA vendors will announce support for the Sugar 2.0 formal property language, adding to a growing list of endorsements that suggests this new Accellera standard will be widely accepted.
2002-09-01	Startups with new ideas In spite of industry consolidation and slowing growth rates, EDA startups are bringing new ideas and technology to chip designers.
2002-06-12	Standards inch forward with skeptics in tow Two standards efforts will take major steps forward at the 39th Design Automation Conference, as the OpenAccess Coalition announces four additional EDA vendor members and much of the EDA community lines up behind Accellera's new SystemVerilog standard.
2004-03-05	Silvaco offers open-source Verilog-A models Silvaco International is offering nine Verilog-A device models for free download under open-source distribution.
2003-04-08	Safelogic VHDL tool sweetened with Sugar Safelogic Verifier 3.1 product now supports PSL.
2003-05-26	New EDA consortium promotes assertion language Seeking to accelerate the adoption of the PSL, 13 EDA companies have joined together with two user companies to form the PSL/Sugar Consortium.
2004-12-01	Methodology sought for assertion-based verification Silicon IP providers and creators seek guidelines on how to use assertions effectively, aside from the standard protocols.