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2004-03-29 Shanghai ICC picks out Aldec as EDA tool provider
Aldec Inc., provider of mixed-language simulation and advanced design tools for ASIC and FPGA devices, has been selected as the recommended verification solution source at the Shanghai IC Center (Shanghai ICC) in China.
2004-11-18 Magma, Aldec deliver front-to-back FPGA design flow
Magma Design Automation Inc. and Aldec Inc. have completed the design flow interface between active-HDL 6.3 and PALACE version 2.4.
2002-09-23 Aldec: Taiwan to drive EDA development in Asia-Pacific region
Taiwan continues to be Asia Pacific's no.1 consumer of EDA tools.
2003-11-07 Aldec, Celoxica offer C-based FPGA design
Providing a mixed HDL and C-based tool suite for FPGA designers, Aldec Inc. and Celoxica Ltd have announced Active-HDL+C.
2003-10-21 Aldec upgrades dual language simulation environment
Aldec has unveiled a new version of its Riviera dual language simulation environment featuring a two-fold performance increase over the previous version.
2006-04-18 Aldec solution increases network-based design verification
Aldec's new mixed-language solution promises to dramatically increase network-based design verification.
2006-05-17 Aldec simulators validated for Lattice devices
Aldec announced that Lattice Semiconductor has validated Aldec's Riviera and Active-HDL simulators for use with Lattice devices.
2006-07-06 Aldec signs up Advinno as ASEAN distributor
Aldec, a supplier of advanced design tools for ASIC and FPGA devices, announced its appointment of Advinno Technologies as their sole distributor for Singapore, Malaysia, Thailand, Philippines and Vietnam.
2002-01-10 Aldec rolls out fast, fully automated FPGA design verification tool
Claimed to be the fastest, most fully automated FPGA design verification tool, Active-HDL 5.1 addresses the latest design trends in the EDA industry, the company says.
2002-05-03 Aldec releases verification software for Xilinx devices
Aldec Inc. has announced the release of the Active-HDL 5.1 XE design software designed specifically for use with high-density Xilinx FPGA devices.
2012-11-09 Aldec ready to tackle Platform Validation topics
Aldec's presentation will cover an overview on transaction-based verification technologies, including SCE-MI macro-based and Direct Programming Interface function-based synthesisable transactors.
2006-03-31 Aldec offers 90-day free access to Riviera Verilog simulator
Aldec announced full simulation support in Riviera for the open-source UltraSPARC T1 from Sun Microsystems.
2006-05-10 Aldec integrates Altera HDL support in simulator
Aldec announced that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment.
2002-06-14 Aldec extends RTL hardware accelerator capacity
Aldec Inc. has announced the availability of the Riviera IPT v12000 functional RTL hardware accelerator that handles up to 12 million FPGA gates.
2006-10-17 Aldec claims Verilog simulation speedup
Aldec's new Riviera-Pro 2006.10 HDL simulator promises to provide a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software.
2005-01-04 Aldec blends SystemC, HDL debugging
Aldec released Riviera 2004.12. New features include integrated SystemC and HDL debugging, assertion-based verification, and functional code coverage.
2005-09-01 Sub-$200 tools power 'farms' for verification
Stanley Hyduke sees a not-so-distant future for the semiconductor industry in which companies are running thousands of simultaneous simulations to cope with the verification bottleneck.
2013-05-22 Spec-TRACER solution tweaked for safety critical designs
Aldec's Spec-TRACER solution is designed to meet certification standards such as DO-254 for avionics, ISO 26262 for automotive, IEC 61508/61511 for industrial and IEC 61513 for nuclear.
2006-07-13 Simulator supports Open IP Encryption design flows
Aldec announced that the new version of its Riviera simulation tool supports design flows based on Synplicity's Open IP Encryption Initiative.
2004-04-13 QuickLogic touts 'power aware' tool
QuickLogic has revealed a "power aware" placement tool for its QuickWorks V9.6 development system.
2003-05-26 FPGA toolset adds C synthesis interface
Bringing C language synthesis to FPGA design, Aldec rolled out its Active-HDL v6.1 toolset.
2004-03-15 EDA tools support new Altera CPLD family
Altera has announced that the new MAX II CPLD device family is supported by much of the EDA industry as well as by Altera's own Quartus II design software.
2007-03-14 Co-verification solution rolls for Actel FPGAs
Aldec has announced the release of CoVer, a Windows-based HW/SW co-verification solution for Actel's ARM-based FPGAs.
2007-05-25 Partnership eases FPGA, PCB design collaboration
To help facilitate collaboration between FPGA and PCB designers, Zuken and Aldec announced a partnership that will make it possible to launch Aldec's FPGA design tools from within Zuken's CR-5000 PCB design environment.
2012-09-19 ASIC prototype system uses Xilinx's Virtex-7
Aldec's HES-7 uses a backplane connector that claims to enable expansion of custom daughter boards or can enable up to four HES-7 boards to interconnect that offers design capacity by up to 96 million ASIC gates.
2001-04-15 Verification firm starts partners program
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry.
2004-10-01 Ventures get capital for a price
There are a lot of startups in EDAprobably too many. If they don't make it, it may sour investors on the sector.
2002-09-16 Unifying software, hardware design environment
Using a unified design environment can help resolve the simulation problems encountered when incorporating new design trends into existing ones.
2004-04-06 Synopsys forum updates SystemVerilog support
The message at the Synopsys EDA Interoperability Developer's Forum, convening Thursday (April 1, 2004), is clear; SystemVerilog support is growing.
2004-04-12 SynaptiCAD joins graphical debugging market
Offering a graphical debugging system that can control Verilog, VHDL, and C++ simulators, SynaptiCAD has announced BugHunter Pro.
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