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2003-08-12 Averant lands patent for checking design properties
RTL verification tool vendor Averant Inc. has been issued a new patent by the USPTO for its method of computing the design coverage of a set of properties.
2003-08-08 Averant lands patent for checking design properties
RTL static functional verification tool vendor Averant has been issued a new patent by the USPTO for its method of computing the design coverage of a set of properties.
2003-03-25 Averant enhances proprietary assertion language
With the new Solidify formal verification tool, Averant Inc. claims to have significantly enhanced its HPL property specification language.
2006-09-18 Averant dives deep into formal verification
Averant took advantage of Design Automation Conference to roll out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification.
2006-07-26 Formal verification tool promises finer control
Averant released the next generation of its formal verification tool, offering what the company claims is the industry's first formal tool to give designers fine control over the tool's thoroughness.
2003-11-03 Formal tool verifies Amba bus protocol
Promising a fast, exhaustive check of interface designs, ARM Ltd and Averant Inc. have announced the SolidAHB static functional verification tool.
2005-03-21 Formal tool able to verify false paths
Real Intent's new software timing-exception prover promises to save designers from a lengthy manual review cycle.
2003-12-01 Formal tool verifies Amba bus protocol
ARM and Averant have announced the SolidAHB static functional verification tool, an add-on to the company's Solidify property verification tool.
2002-03-13 Vendors join push for assertion standards
The strongest effort yet to forge a standard assertion language for IC verification will unfold at the International HDL Conference this week, as Co-Design Automation and Real Intent announce the donation of the Superlog Design Assertion Subset to the Accellera standards body.
2004-03-17 Tool pinpoints false paths, steers designers away
FishTail Design Automation is targeting what sounds like a small niche, but the company says the potential benefits of its technology are huge.
2005-07-01 Analog EDA firm tackles PLL noise
Berkeley's PLL noise analyzer promises to shrink time-to-volume for discrete analog/RF chips and SoCs containing analog blocks.
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