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2009-01-22 BER reference design rolls for 100G Ethernet testing
Inphi Corp. has launched a 28G Bit Error Ratio (BER) Receiver reference design for R&D or production testing of emerging high speed protocols.
2014-11-12 Determine acceptable jitter level in embedded design
Learn about the nuances of clock jitter specifications, and know how to determine the acceptable level of jitter early on in the development cycle to prevent dire impact on end product release schedules.
2011-11-17 Address challenges in 40G/100G SerDes design, implementation
Read about the various aspects of SerDes design such as transmit/receive portions
2007-06-28 Build WiMAX base stations, subscriber stations
Designing for WiMAX requires an understanding of the newest MAC and PHY features for fixed WiMAX systems and applications.
2006-05-16 Tips for maximizing RapidIO
RapidIO is an open, standards-based interconnection technology for midsize and large embedded systems. Travis Scheckel discusses tips for designers working with it for the first time.
2003-12-09 Toshiba module supports air data rates of up to 1Mbps
Toshiba America Electronic Components Inc. has announced the addition of a 2.4GHz RF transceiver module that can be used as an embedded reference design for the TB32301AFL radio transceiver
2008-05-15 Serdes chipset claims 'best' jitter performance
National Semiconductor has introduced a Serdes chipset that the company claims delivers the industry's best output jitter performance of 35ps peak-to-peak and the best input jitter tolerance of 0.9 UI with a BER of 10-15
2015-10-06 Low-jitter clock generators boost reliability in telco apps
TI said the LMK033x8 allows system designers to optimise system timing margins and BER to cut data transmission errors, allowing more reliable networking, server and computing industrial equipment
2012-01-04 Boost SDR performance
Here are some examples of how software for system simulation of RF end-to-end architecture design can be used to address the software defined radio design challenges
2011-12-23 Address 4G issues with SystemVue
A number of EDA tools available on the market today can be used for LTE-based design; however, creating systems designs for the emerging LTE-A standard requires an entirely new set of functionality
2008-05-13 RFMD launches 2.4GHz ISM band transceiver
RF Micro Devices has introduced the ML2726 ISM band transceiver, a low power, low-IF, frequency shift key transceiver designed for operation in the license-free 2.4GHz ISM band.
2009-02-27 IC family claims improved RF performance
A new IC family from Silicon Laboratories Inc. claims improved RF performance for both the transmit and receive paths, as well as internal functions which significantly off-load the companion MCU and minimize overhead.
2008-04-22 VCSO has expanded frequency range, ultralow jitter
The VS-705 VCSO from Vectron International delivers new and improved features including an expanded frequency range and power management capabilities that support "green" initiatives.
2008-02-18 Use UWB in ultralow-power Zigbee sensor nodes
The IEEE 802.15.4 standardization committee who defined the MAC and PHY adopted by Zigbee has proposed an alternative PHY relying on UWB technology.
2004-09-24 Tektronix package delivers fast, accurate measurements
Tektronix's TDSJIT3 v2 is a software package that promises to deliver fast, accurate and easy to use jitter and timing measurements.
2015-07-10 Jitter concerns when selecting timing solutions
Determining the effects of jitter on the system, as well as defining the jitter budgets for the various sub-systems are the keys to optimising system performance.
2008-09-16 Jedec spec standardizes 8B/10B gains
IBM Corp.'s 8B/10B makes single transmission-line-pair communications possible at frequencies above 2GHz. Jedec specification JESD204 defines the protocol and electrical characteristics required to standardize the implementation of this coded interface for data converters, enabling a new generation of faster and more accurate serial ADCs.
2014-10-16 How to improve FPGA comms interface clock jitters
Know how external phase locked loops can be used to resolve problems faced when dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes.
2014-11-27 How to achieve 200-400GE network buffer speeds
Know how a serial chip-to-chip protocol, with 200-400 GE data rates and 4.5 B read/write transactions, can be used to eliminate throughput bottlenecks at the processor/external DDR memory interface.
2013-12-30 Examining JESD204B converter protocol advances
JESD204 was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
2005-06-01 Driving 10Gb Serial ATCA backplanes
The Backplane Ethernet Task Force is focused on developing three new PHYs: 1000BASE-KX, 10GBASE-KX4 and 10GBASE-KR
2009-04-28 Clock generators achieves 500fs RMS jitter
Texas Instruments Inc. has unveiled three new precision clock generators that have a crystal input, replacing up to four discrete high-frequency crystal oscillators with a single device.
2005-05-27 Clock extraction circuitry times high-speed communications test
What you need to know when testing digital communications systems.
2016-05-18 Benefits of adding isolation to LVDS interfaces
Adding isolation to LVDS interfaces provides a transparent solution that can be inserted into existing signal chains for high-speed and precision measurement and control applications.
2013-06-11 Address jitter, noise with DDR4 (Part 2)
Learn about the DDR4 eye mask and how it can be used to improve designs.
2002-06-16 10GbE standard clears major hurdle for optical transceivers
Learn more about the breakthroughs and the drawbacks of developing the new Gigabit Ethernet standard for optical transceiver systems.
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