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| 2005-02-01 | Bluespec synthesizes SystemVerilog verification assertions The startup has announced its ability to synthesize SystemVerilog verification assertions into Verilog 1995 RTL code. |
| 2006-11-29 | Virtual prototype support rolls out Bluespec Inc. will roll out within the week a new version of its Bluesim simulator that supports virtual prototyping for software development and hardware validation. |
| 2007-02-08 | Reusable IP enhances ESL synthesis Bluespec's AzureIP library brings reusable IP to an ESL synthesis tool that starts at a much higher level of abstraction and produces RTL code. |
| 2004-03-25 | MIT technology fuels startup's synthesis tool EDA startup Bluespec Inc. this week will announce an exclusive license from the Massachusetts Institute of Technology (MIT) for synthesis technology based on term rewriting systems (TRS). |
| 2003-12-09 | EDA startup pioneers assertion-based synthesis Startup Bluespec Inc. will preview an "assertion-based" synthesis technology next week that it describes as a new approach to chip design. |
| 2007-04-16 | AzureIP library accelerates ESL synthesis Claiming to set a new direction for silicon intellectual-property (IP) design and reuse, Bluespec Inc. has rolled out the AzureIP Foundation Library, a set of parameterized IP blocks for use with the company's Bluespec Compiler. |
| 2007-01-16 | New Bluesim supports virtual prototyping Targeting an emerging niche within ESL design, Bluespec Inc. rolled out a new version of its Bluesim simulator that supports virtual prototyping for software development and hardware validation. |
| 2006-04-17 | Vendors warm to SystemVerilog Despite Synopsys' skepticism, synthesis vendors appear strongly supportive of a proposed standard SystemVerilog synthesis subset. |
| 2004-02-02 | Synopsys, Cadence give nod to SystemVerilog changes Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a. |
| 2004-04-06 | Synopsys forum updates SystemVerilog support The message at the Synopsys EDA Interoperability Developer's Forum, convening Thursday (April 1, 2004), is clear; SystemVerilog support is growing. |
| 2006-03-20 | Initiative launched to accelerate FPGA system level design adoption Xilinx launched the ESL Initiative, a multi-faceted program aimed at making ESL design methodologies and tools more accessible to programmable system designers. |
| 2010-12-24 | Design methods shift to software, part 2 Designing via block level IP integration with virtual platforms shortens the number of steps between design intent and having working hardware and software. |
| 2004-06-01 | Behavioral synthesis crossroad Ten years after its market entry as the next generation in synthesis, Synopsys' Behavioral Compiler is dead. Can somebody else breathe new life into behavioral synthesis? |
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