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2006-11-16 'DFM too complex,' experts say
Speakers told the Bacus Photomask Technology Symposium that DFM technology is too complex and suggested the use of standardized layout elements, library cells or an "integrated" DFM methodology.
2013-07-22 Virtual design, verification for e-Mobility
Learn how to address many of the emerging engineering challenges that carmakers now face.
2002-04-04 Technical program assembled for upcoming DAC
Hoping to convince designers that this year's Design Automation Conference is worth the trek to New Orleans, the show's committees have announced an innovative technical program.
2005-03-17 Synopsys unveils 'next-gen' compiler for physical design
Synopsys unveiled a physical design solution, which the company claims provides leading-edge performance and already carries endorsements by key IC suppliers.
2005-04-18 Synopsys unveils 'next-gen' compiler
The company introduces a physical design solution which it says provides concurrent clock tree synthesis, routing and yield optimization.
2015-06-22 Synopsys rolls out latest photonics design tools
The RSoft 2015.06 release promises to facilitate faster, more efficient design of various current and emerging photonic devices, photonic circuits and fibre-based applications.
2004-04-30 Synopsys keynoter cites crosstalk, power challenges
Crosstalk and power are extremely difficult problems to solve, and will require significant changes to the existing chip design flow, according to Li-Pen Yuan, R&D director for extraction and signal integrity at Synopsys.
2006-05-01 Summit Design offers 'personal edition' of SystemC IDE on Web
The Vista-PE, touting all the features of the full-fledged Vista IDE at the module level, hopes to help people bring up and explore SystemC.
2006-10-16 Startups take on analog design automation
Automating analog IC design has proven to be a tough challenge, but two EDA startups are promising to do just that with a new "analog synthesis" technology.
2002-05-02 Startup promises automated cell optimization
Electronic design automation startup Zenasis Technologies Inc. wants to bring the precision of full-custom design to ASIC and system-on-chip design with a cell-optimization technology it plans to release sometime next year.
2006-05-29 ST certifies Mentor Catapult C Synthesis Libraries
Mentor Graphics announced that STMicroelectronics has added Catapult C Synthesis libraries to its standard ASIC design kit.
2008-08-25 Spice model shapes up organic TFT panels
Cambridge Display Technology has collaborated with Silvaco Data Systems to develop Spice model for organic TFT technology.
2013-02-06 Solving SoC and FPGA prototyping debug issues
Read about the accelerated development, verification and debugging of ASIC hardware and software.
2007-08-23 Software tests wireless devices for hearing-aid compatibility
Agilent's new Antenna Modeling Design System software contains new capabilities to verify that handheld wireless devices are compatible with hearing aids.
2001-06-01 Scripts bind EDA tools
Different EDA recommendations/innovations are emerging to answer the needs of manufacturers and OEMs.
2013-01-25 Reduce power estimation time from weeks to hours
Find out how to automatically generate a chip design's gate-level waveform from the RTL design environment without having to bring up the gate-level environment.
2008-08-19 On-demand service caters to design engineers
Aligni has claimed the industry's first on-demand, Web-based parts, components, and inventory management service created specifically for design engineers.
2009-10-14 NREL adopts Synopsys TCAD for solar cells
The U.S. National Renewable Energy Laboratory has selected Synopsys' Sentaurus TCAD to create solar cell models.
2010-09-24 New testing solutions for PCB manufacturers
Digitaltest GmbH expands line of testing solutions
2008-08-01 Multithreading comes undone
EDA vendors have struggled to meet the challenge of multicore IC design by rolling out multithreading capabilities for their tools. Nonetheless, the question cannot be ignored: Is multithreading the best way to exploit multicore systems effectively?
2004-06-10 Mentor, Cadence share most top honors in PCB study
Mentor Graphics and Cadence Design Systems took the lion's share of top honors in a PCB EDA survey, but Agilent EEsof garnered the top spot in customer satisfaction.
2005-10-10 Mentor making automotive EDA push
Looking to push its widely acknowledged lead in the automotive EDA space, Mentor Graphics Corp. Thursday (Oct. 6) announced a major new automotive design push.
2006-10-25 Mentor intros next-generation harness design
Mentor Graphics Corp. introduced Capital HarnessXC, its next-generation harness design solution for electrical wire harness design and engineering in planes, trains and automobiles.
2007-10-09 Master the I/O planning puzzle
Systemwide I/O planning is an exercise in coordinating device placement with associated pin and net assignments across the chip-package-board system to maximize system quality for the target application. Achieving this goal is a multidomain balancing act of tradeoffs and iterations.
2009-03-04 Make engineering fun for kids
This is my story about how I got a second chance and went on to develop a computer game to make and keep engineering fun for students in the middle school and high school grades.
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications.
2005-08-26 Is automotive industry the 'next big wave' for EDA?
Largely missed in the rubble after Mentor Graphics Corp. slashed second half guidance following disappointing second quarter bookings last month was a statement by Chairman and CEO Walden Rhines that could offer a ray of future hope for the company and the EDA industry as a whole.
2013-03-06 Impact of the Cloud on FPGA design
Know the benefits and potential pitfalls of cloud computing in FPGA design from a practical, day-to-day viewpoint.
2007-06-01 IC designers favor less complex DFM
During the IEEE Electronic Design Process workshop, IC design experts point out that current approaches to design-for-manufacturing (DFM) may be yielding too little for the amount of effort and cost involved.
2009-01-13 How will Tan lead Cadence's resurgence?
Cadence's board appointed one of its own to the top job, saddling him with the daunting task of leading Cadence's resurrection.
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