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2008-09-15 Tensilica, Cadence tip CPF-enabled multimedia designer
Tensilica Inc. and Cadence have collaborated to create a Common Power Format (CPF)-enabled low-power reference design for a multimedia subsystem based upon its popular 330HiFi audio processor and 388VDO video engine
2006-10-16 Power standard standoff reaches stalemate
Participants behind two rival efforts to define a standard IC power description format are attempting to make their initiatives more inclusive
2008-01-24 Japan's Starc uses Cadence's CPF tech in ref flow
Cadence Design Systems announced that Japan's Starc has released its next-generation ultralow-power Pride reference flow V1.5, incorporating the CPF-based Cadence Low-Power Solution
2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools.
2006-11-06 Cadence, Si2 team up for unified low-power standard
Cadence and Silicon Integration Initiative partnered to enable a common industry standard for low-power design, implementation and verificationthe Common Power Format
2007-02-01 Cadence deploys CPF in low-power design flow
Cadence Design Systems has added the Common Power Format (CPF) to its existing logic design, verification and implementation tools
2007-04-20 UMC joins Power Forward Initiative
Semiconductor foundry UMC is the newest member of the Power Forward Initiative, an alliance of over 20 companies that aims to advance the adoption of the Common Power Format standard for low power design
2008-07-14 Japanese design services firms sign up for PFI
Three Japanese design services company have recently joined the Power Forward Initiative (PFI), and they will be offering Common Power Format (CPF)-enabled low-power design capabilities to their customers
2006-12-01 EDA vendor rivalry bogs single power spec
Amid calls for a single power spec throughout the design flow, EDA vendor rivalry continues to fuel two separate efforts to develop a low-power description standard
2007-02-27 EDA 'troublemakers' debate at DVCon
Confronted with provocative questions, DVCon EDA vendor representatives debated topics such as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India.
2008-11-03 A less visible, yet important, ballot is underway: P1801
In The Standards Game, there is another important ballot underway: IEEE P1801, formally known as the "Standard for Design and Verification of Low Power Integrated Circuits
2009-02-13 What's in store for P1801 (Unified Power Format)?
A common industry standard for low power design and verification will satisfy what customers have needed all along
2008-05-14 VeriSilicon signs up with Power Forward Initiative
VeriSilicon has joined the Power Forward Initiative and plans to offer a CPF-based design solution for its ASIC customers
2007-03-27 The dilemma of two languages in low-power design
EDA users may not like it, but when it comes to low-power design they will probably have to speak two languages: CPF and UPF
2007-05-01 Hope dims for power spec merger
Two rival specification formats for low-power IC design are now publicly available, and backers of both agree that it would be technically feasible to converge them into a single standard. But disagreements over how that convergence should take place threaten to block further progress
2006-09-18 EDA rivals spar over power issues
Any EDA vendor or large EDA user will tell you there's a compelling need for a standard way to express power-management intent throughout the IC design flow. The problem is that two separate groups are working toward that objective, amid profound disagreements over how to get there
2009-07-28 Power to take center stage at DAC
Power, arguably today's No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks at the 46th Design Automation Conference (DAC).
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node.
2007-07-16 TSMC pulls curtains off 45nm design process
Taiwan Semiconductor Manufacturing Co. Ltd unveiled its latest and most ambitious design methodology for IC production at the challenging 45nm node.
2008-02-26 Rhines on EDA: End 'endless verification'
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2013-06-10 Power manager for Mindspeed's Comcerto 2000 comms processor
AGGIOS and Mindspeed Technologies released the AGGIOS CLIOS Power Manager that claims to achieve the lowest power states and shortest wake-up times for optimal whole-system power management.
2009-03-19 Power management for optimal design
This article describes a holistic approach for managing and optimizing the power in a design. Effective power management involves proper understanding the application of a chip, technology selection, design techniques and methodology.
2008-05-05 Power Forward Initiative gets MindTree onboard
MindTree has joined the Power Forward Initiative and will be offering a Common Power Format-enabled low-power flow to its design services customers.
2012-06-18 Managing power islands on chips
Read about the use of power-aware emulation to verify the logic-level robustness of an SoC in the face of power changes.
2007-03-23 Hope fades for IC power standards union
The hoped-for-convergence between two rival IC low-power specifications will not likely take place anytime soon.
2008-05-30 Faraday, NemoChips develop low power mobile platform
Faraday Technology Corp. and NemoChip have partnered to develop next-generation low power mobile platform based on Cadence Low-Power Solution.
2012-10-19 Employ hierarchical methods for power intent specification
Here's a guide to using a hierarchical low-power design methodology.
2008-02-18 Cadence identifies Asia's EDA growth factors
How is Asia's EDA industry faring? Lung Chu, Cadence Design Systems Asia Ltd's Asia Pacific president, shares the region's EDA growth information, bares his thoughts on the key places of development and discusses the company's efforts for low-power design.
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification.
2011-10-12 A practical way of inspecting IP quality
Find out how to set up a process which can give you solid incoming IP quality inspectiona process that quite likely finds potential problems you may not have checked before, all with a minimum of overhead both in maintenance and in cycle time.
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