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2003-09-10 Xilinx upgrades ISE FPGA design suite
Xilinx Inc. has improved clock performance, software run-time and area utilization in its Integrated Software Environment FPGA design suite
2005-03-21 Wipro, Cadence renew EDA agreement
Tapping into a growing Indian IC design market, Cadence Design Systems Inc. has renewed an agreement giving India-based Wipro Technologies access to its EDA software.
2003-03-13 TTPCom acquires Cadence 802.11 WLAN IP
TTP Communications plc has acquired full ownership of the 802.11 WLAN intellectual property developed by Cadence Design Systems Inc.
2007-06-28 TSMC, Cadence team on 65nm wireless design flow
Cadence and TSMC have teamed on nanometer wireless design and produced a new TSMC 65nm RF PDK compatible with the new Cadence Virtuoso custom design platform
2004-04-19 TSMC, Cadence disclose reference flow integration plan
Taiwan Semiconductor Mfg Co. Ltd (TSMC) and Cadence Design Systems Inc. have announced their planned integration of Cadence Encounter RTL Compiler into TSMC's next-generation reference flow.
2005-06-13 TSMC releases reference design flow for 65nm processes
Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes.
2006-07-20 TSMC reference flow integrates Cadence platforms
Cadence and TSMC announced the integration of the Cadence's Encounter digital IC design platform and Allegro system interconnect platform into TSMC's Reference Flow 7.0
2007-07-16 TSMC pulls curtains off 45nm design process
Taiwan Semiconductor Manufacturing Co. Ltd unveiled its latest and most ambitious design methodology for IC production at the challenging 45nm node
2003-06-04 TSMC latest reference flow adopts Cadence platform
TSMC has selected Cadence Design Systems Inc.'s Encounter digital IC design platform as an integral part of TSMC's latest Reference Flow 4.0.
2005-10-06 TSMC approves X Architecture design
Taiwan Semiconductor Manufacturing Company (TSMC) disclosed on Oct. 4 that they are ready to accept 90nm X Architecture designs.
2005-01-27 Tower Semiconductor strengthens design center program
Tower Semiconductor Ltd announced a major expansion of the Tower Authorized Design Center (TADC) program, naming Cadence Design Systems Inc., QThink, QualCore Logic and SliceX as design center partners.
2002-08-01 Toumaz design flows based on Cadence tools
Toumaz Technology Ltd is developing AMx systems with front-to-back analog design flows based on the tools and methodology services by Cadence Design Systems Inc.
2008-01-31 Toshiba, Cadence collaborate on 65nm design
Cadence Design announced that Toshiba has deployed Cadence Virtuoso simulation technology to provide its analog and mixed-signal chip designers an easy-to-use and accurate reliability analysis flow
2004-12-21 Toshiba supports Cadence RTL compiler for ASIC design
Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis.
2006-08-30 Toshiba adopts Cadence solution for 65nm design
Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows
2006-02-23 Tool generates verification plans from design specs
Severity One is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface.
2002-08-09 TI deploys Cadence verification systems
TI has installed the Palladium design verification systems of Quickturn through the QuickCycles EXtended (EX) Access program
2003-01-08 Tharas signs ICON Design as distributor in India
Tharas Systems Inc. has named ICON Design Automation Pvt. Ltd as its distributor in India
2005-08-31 Tensilica enhances methodology for 90nm design flow
Tensilica has enhanced its automated configurable processor design methodology to account for common IC design challenges with 90nm process technology
2007-02-21 SystemVerilog falls short for design
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support
2004-04-02 SystemC tool adds top-down design
CoWare has added graphics-based front-end design software and other features to the System Designer tool of ConvergenSC
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2004-05-03 Startup looks to fill Cadence CCT vacuum
ConnectEDA aims to fill a gap left when Cadence stopped making its CCT autorouter available for sale by competing EDA vendors in the late 1990s
2011-02-07 Solution speeds billion-plus gate design at 28nm
Cadence Design Systems Inc. has announced that it is advancing the design of giga-gate/gigahertz SoCs with digital end-to-end flow at 28nm.
2010-12-06 SMIC chooses Cadence for 65-nm reference flow
Cadence Design Systems, Inc., has just announced that SMIC has adopted Cadence Silicon Realization products for the DFM and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1.
2002-08-29 SiS adopts Cadence technology for graphics IC design
Silicon Integrated Systems Corp. has standardized on Cadence Design Systems Inc.'s First Encounter, for the design of complex graphics ICs.
2006-02-08 Sirific used Cadence's simulator in designing its RF transceiver
Cadence announced that Sirific has designed its single-chip CMOS RF transceiver for HSDPA/WEDGE using Cadence's Virtuoso UltraSim Full-chip Simulator for FastSPICE simulation
2002-04-29 Simplex purchase expands Cadence's technology trove
In announcing its intention to purchase Simplex Solutions, Cadence Design Systems has set its sights on some key EDA and silicon architecture technology
2015-10-20 Sensory brings face authentication software to Cadence DSPs
Cadence and Sensory said the technology makes it easier for mobile designers to cut the power needed for face authentication to unlock a mobile phone, tablet, or any IoT device using a standard camera
2012-02-10 Samsung, Cadence partner in nanometer SoC design
The companies will collaborate on a design-for-manufacturing (DFM) infrastructure to tackle physical signoff and electrical variability optimization for 32, 28 and 20nm ICs
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