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2005-08-02 Global UniChip improves silicon quality with Cadence tech
Cadence Design Systems Inc. disclosed that Taiwan-based Global UniChip Corp. has adopted Cadence Encounter RTL compiler global synthesis, part of the Encounter digital IC design platform, to improve the quality of silicon (QoS) of its hardened IP.
2005-12-08 Cadence upgrades Encounter RTL compiler
Cadence announced an upgraded version of its Cadence Encounter RTL Compiler global synthesis technology that helps designers deliver smaller, faster and cooler chips in less time.
2006-07-20 TSMC reference flow integrates Cadence platforms
Cadence and TSMC announced the integration of the Cadence's Encounter digital IC design platform and Allegro system interconnect platform into TSMC's Reference Flow 7.0
2008-09-15 Tensilica, Cadence tip CPF-enabled multimedia designer
Tensilica Inc. and Cadence have collaborated to create a Common Power Format (CPF)-enabled low-power reference design for a multimedia subsystem based upon its popular 330HiFi audio processor and 388VDO video engine
2005-12-20 Inphi tapes out high-speed chip with Cadence platform
Cadence announced that Inphi has successfully taped out a complex high-speed chip using the Cadence Encounter digital IC design platform
2005-12-22 Faraday tapes out ASIC production chips with Cadence platform
Cadence announced that Faraday has taped out ten 130nm ASIC production chips with the Cadence Encounter digital IC design platform
2006-11-15 Cadence teams with IBM to accelerate ASIC design
Cadence Design Systems has inked an agreement with IBM to incorporate Encounter RTL Compiler global synthesis and Cadence Encounter Test technologies into IBM's 65nm ASIC design kit.
2004-12-23 Cadence RTL Compiler supports Oki Soc design platform
Cadence Design Systems Inc. announced that Oki Electric Ind. Co. Ltd has taped out a chip for Oki's uPLAT SoC design platform with the new low-power capability of Cadence Encounter RTL Compiler synthesis
2006-12-21 RTL synthesis tool speeds up run-time
Cadence Design Systems has released Encounter RTL Compiler version 6.2, which promises a 10 percent improvement in quality of silicon and a 30 to 50 percent run-time speedup
2007-07-11 RTL synthesis tool eases chip-level interconnect design
Claiming a new approach that helps solve problems with chip-level interconnect, Cadence Design Systems is announcing a new component of its RTL synthesis tool, the Cadence Logic Design Team Solution
2006-01-26 Fujitsu adopts Cadence Encounter GXL
Cadence announced that Fujitsu has adopted its Encounter digital IC design platform in its new internal reference design flow targeted at 65-nanometer chips
2004-09-10 Cadence, UMC create sub-130nm IC reference flow
Cadence Design Systems Inc. and foundry United Microelectronics Corp. have announced an RTL-to GDSII reference flow for digital IC designs implemented in UMC's 130nm and lower processes
2007-12-12 Cadence, ARM co-develop multicore ref design kits
Cadence Design Systems Inc. and ARM have jointly developed reference methodologies, one for the ARM11 MPCore multicore processor and the other for low-power implementation of the ARM1176JZF-S processor
2004-02-20 Cadence rolls synthesis tool, new metric
Cadence Design Systems will announce that its Encounter RTL Compiler Ultra synthesis tool supports the VHDL language
2005-07-22 Cadence Encounter RTL to perform Canon's future tapeouts
Cadence Design Systems Inc. announced that Japan-based Canon Inc. has adopted its Encounter RTL compiler for ASIC designs
2005-05-27 EDA vendors announce flows for IBM-Chartered 90nm process
IBM and Chartered Semiconductor Mfg added common design support to their jointly developed 90nm process platform.
2011-01-20 32/28-nm reference flow for Common Platform Alliance ushered
Cadence's 32/28nm Low-Power RTL-to-GDSII Silicon Realization Reference features new design intent, abstraction and convergence capabilities giving more deterministic path to advanced silicon
2007-07-16 Multicore reshapes EDA landscape
The largest EDA vendors acknowledge that the advent of multicore processors is a cause for both celebration and concern. Multicore platforms will provide much-needed compute power as transistor counts soar at 65nm and below. But legacy applications could prove difficult or even impossible to parallelize.
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