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2005-03-21 Wipro, Cadence renew EDA agreement
Tapping into a growing Indian IC design market, Cadence Design Systems Inc. has renewed an agreement giving India-based Wipro Technologies access to its EDA software.
2006-12-15 Wipro selects Cadence as primary VLSI vendor
Wipro Technologies, a global independent R&D services provider and the services arm of Wipro Ltd, has chosen Cadence Design Systems as its primary vendor for VLSI and system design solutions.
2007-08-02 Winbond adopts Cadence emulator to ease verification
Cadence Design Systems announced that Winbond Israel has adopted the Cadence Incisive Palladium emulator system for its advanced system-level verification needs.
2008-07-25 What has driven Cadence to buyout Mentor?
Although I have heard from a few financial analysts who think the acquisition is good for Cadence and for the industry, I continue to believe it will not work even if classical investment theory says it should.
2013-07-18 UMC adopts Cadence's DFM flows for 28nm node
The flows address both random and systematic yield issues and incorporate DFM prevention, analysis, and signoff capabilities.
2003-03-13 TTPCom acquires Cadence 802.11 WLAN IP
TTP Communications plc has acquired full ownership of the 802.11 WLAN intellectual property developed by Cadence Design Systems Inc.
2007-06-28 TSMC, Cadence team on 65nm wireless design flow
Cadence and TSMC have teamed on nanometer wireless design and produced a new TSMC 65nm RF PDK compatible with the new Cadence Virtuoso custom design platform.
2004-04-19 TSMC, Cadence disclose reference flow integration plan
Taiwan Semiconductor Mfg Co. Ltd (TSMC) and Cadence Design Systems Inc. have announced their planned integration of Cadence Encounter RTL Compiler into TSMC's next-generation reference flow.
2006-07-20 TSMC reference flow integrates Cadence platforms
Cadence and TSMC announced the integration of the Cadence's Encounter digital IC design platform and Allegro system interconnect platform into TSMC's Reference Flow 7.0.
2003-06-04 TSMC latest reference flow adopts Cadence platform
TSMC has selected Cadence Design Systems Inc.'s Encounter digital IC design platform as an integral part of TSMC's latest Reference Flow 4.0.
2002-05-30 TSMC adopts Cadence's signal analysis for reference design flow
Taiwan Semiconductor Mfg Co. has adopted Cadence Design System Inc.'s CeltIC signal-integrity analysis solution for its 0.135m reference design flow.
2012-05-18 TowerJazz reference design flow tips Cadence tech for power management
TowerJazz's Reference Flow 2.0 power management analog/mixed-signal reference design flow integrates power management devices with control logic.
2002-08-01 Toumaz design flows based on Cadence tools
Toumaz Technology Ltd is developing AMx systems with front-to-back analog design flows based on the tools and methodology services by Cadence Design Systems Inc.
2008-01-31 Toshiba, Cadence collaborate on 65nm design
Cadence Design announced that Toshiba has deployed Cadence Virtuoso simulation technology to provide its analog and mixed-signal chip designers an easy-to-use and accurate reliability analysis flow.
2004-12-21 Toshiba supports Cadence RTL compiler for ASIC design
Cadence Design Systems Inc. announced that Toshiba America Electronic Components Inc. (TAEC) has introduced a design kit to support its custom System-on-Chip (SoC) and ASIC customers using Cadence Encounter RTL compiler synthesis.
2006-08-30 Toshiba adopts Cadence solution for 65nm design
Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows.
2002-08-09 TI deploys Cadence verification systems
TI has installed the Palladium design verification systems of Quickturn through the QuickCycles EXtended (EX) Access program.
2008-09-15 Tensilica, Cadence tip CPF-enabled multimedia designer
Tensilica Inc. and Cadence have collaborated to create a Common Power Format (CPF)-enabled low-power reference design for a multimedia subsystem based upon its popular 330HiFi audio processor and 388VDO video engine.
2001-03-20 Targeting Cypress PLDs from the Cadence environment
This application note discusses the procedures in targeting the designs of Cypress Semiconductor's PLDs from the Cadence software bolt-in software program kit.
2004-02-02 Synopsys, Cadence give nod to SystemVerilog changes
Enhancements based on feedbacks from vendors and users spotlighting some shortcomings in the current ver 3.1, will be implemented in SystemVerilog 3.1a.
2005-01-04 Sun, Cadence partner with Indian firm for VLSI training
Sun Microsytems and Cadence Design have partnered with Veda Institute of Information Technology, based in Hyderabad in southern India, to start the country's first nodal center of competency for research and development in VLSI engineering, design automation and embedded system engineering.
2004-12-30 Sun, Cadence partner with Indian firm for VLSI training
Sun Microsytems and Cadence Design have partnered with Veda Institute of Information Technology, based in Hyderabad in southern India, to start the country's first nodal center of competency for research and development in VLSI engineering, design automation and embedded system engineering.
2004-05-03 Startup looks to fill Cadence CCT vacuum
ConnectEDA aims to fill a gap left when Cadence stopped making its CCT autorouter available for sale by competing EDA vendors in the late 1990s.
2013-07-31 ST, ARM and Cadence team up for tool, model interoperability
The collaboration of ST, ARM and Cadence aims to increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level.
2010-09-20 SMIC taps Cadence for design solutions
Cadence offers front-to-back solutions for design, verification and implementation
2010-12-06 SMIC chooses Cadence for 65-nm reference flow
Cadence Design Systems, Inc., has just announced that SMIC has adopted Cadence Silicon Realization products for the DFM and low-power technology at the center of SMIC's 65-nanometer Reference Flow 4.1.
2002-08-29 SiS adopts Cadence technology for graphics IC design
Silicon Integrated Systems Corp. has standardized on Cadence Design Systems Inc.'s First Encounter, for the design of complex graphics ICs.
2006-02-08 Sirific used Cadence's simulator in designing its RF transceiver
Cadence announced that Sirific has designed its single-chip CMOS RF transceiver for HSDPA/WEDGE using Cadence's Virtuoso UltraSim Full-chip Simulator for FastSPICE simulation.
2002-04-29 Simplex purchase expands Cadence's technology trove
In announcing its intention to purchase Simplex Solutions, Cadence Design Systems has set its sights on some key EDA and silicon architecture technology.
2015-10-20 Sensory brings face authentication software to Cadence DSPs
Cadence and Sensory said the technology makes it easier for mobile designers to cut the power needed for face authentication to unlock a mobile phone, tablet, or any IoT device using a standard camera.
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