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total search20 articles
2005-05-11 Verific Design licenses HDL component software to Calypto
Calypto Design Systems Inc. has licensed Verific Design Automation's hardware description language (HDL) component software.
2006-02-01 Vendor sees ESL design taking hold
Adoption of ESL design methodology in North America has accelerated in recent months. Japan remains strongest in ESL because designers in Japan had a head start, showing interest in ESL the earliest
2007-08-01 Increase design productivity by leveraging ESL techniques
ESL is changing the way designs are done. With a good understanding of software programming, engineers armed with ESL tools are moving design to the next level of productivity
2014-12-04 Calypto intros high-level synthesis tech to speed up design
The Catapult 8 with the configurable hierarchical design architecture is built on a completely revised architecture that expedites design and verification closure, pushing widespread adoption of HLS
2011-08-31 Calypto acquires Catapult C for better integrated ESL flow
Aiming to get all as many pieces of an integrated ESL design flow together, Calypto said it has acquired, in a yet undisclosed terms, Catapult C Synthesis from Mentor
2010-12-24 Design methods shift to software, part 2
Designing via block level IP integration with virtual platforms shortens the number of steps between design intent and having working hardware and software
2008-07-03 Confab stresses potential thermal crisis in IC design
At the Design Automation Conference in Anaheim, California, an educational panel addressed the thermal issue in IC design. Two key questions raised were when will this issue be emerging as a crucial concern? What are the solutions to solve this potential crisis
2005-06-06 Startup integrates equivalence checker with Mentor's Catapult
Calypto Design Systems Inc. said that it would work with Mentor Graphics Corp. to facilitate integration between Calypto's system-level equivalence checker (SLEC) and Mentor's Catapult C synthesis tool
2006-11-08 Equivalence checker eyes clock gating
The sequential equivalence checker that Calypto Design Systems will release soon promises to automate the verification of clock-gating circuitry.
2005-01-21 EDA startup preps sequential equivalency checker
Promising to ensure that high-level models match their RTL implementations, startup Calypto Design Systems announced its mission and its plans to field a sequential equivalency checker.
2008-06-02 Use system models for better verification
This article describes the system-level to RTL design and verification flow of a commercial graphics processing chip. In this flow, system models were developed to validate the arithmetic computation of video instructions and were then used to verify the RTL implementation using sequential logic equivalence checking
2007-03-28 Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code.
2015-03-30 Significance of RTL architecture to power analysis
Learn about the advantages of a well defined RTL architecture for power estimation and analysis through a case study of a FIFO design
2009-09-02 Sequential analysis ensures accurate power measurement
Calypto Design Systems Inc. has developed what it touts to be the most accurate register-transfer level (RTL) power analysis capability by applying its patented sequential analysis technology.
2011-05-31 Power optimization tool reduces power by 60%
Calypto has released version 5.0 of its PowerPro Platform, featuring new RTL power analysis capabilities
2005-01-19 EDA startup preps sequential equivalency checker
Promising to ensure that high-level models match their RTL implementations, startup Calypto Design Systems this week is announcing its mission and its plans to field a sequential equivalency checker.
2005-10-27 Survey finds verification tool use largely unchanged from 2004
The 2005
2006-10-16 Power standard standoff reaches stalemate
Participants behind two rival efforts to define a standard IC power description format are attempting to make their initiatives more inclusive.
2007-07-16 Multicore reshapes EDA landscape
The largest EDA vendors acknowledge that the advent of multicore processors is a cause for both celebration and concern. Multicore platforms will provide much-needed compute power as transistor counts soar at 65nm and below. But legacy applications could prove difficult or even impossible to parallelize.
2005-01-21 Startup claims to optimize IC layouts for yield
Even the best chip layouts need some help to maximize IC yields, according to startup Nannor Technologies Inc., which is quietly preparing a layout optimization tool.
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