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2008-05-14 VeriSilicon signs up with Power Forward Initiative
VeriSilicon has joined the Power Forward Initiative and plans to offer a CPF-based design solution for its ASIC customers
2007-04-20 UMC joins Power Forward Initiative
Semiconductor foundry UMC is the newest member of the Power Forward Initiative, an alliance of over 20 companies that aims to advance the adoption of the Common Power Format standard for low power design.
2007-03-27 The dilemma of two languages in low-power design
EDA users may not like it, but when it comes to low-power design they will probably have to speak two languages: CPF and UPF
2009-03-18 Solution supports on-chip power management
Cadence Design Systems Inc. has enhanced the Cadence Low-Power Solution to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power Format (CPF) Version 1.1.
2006-10-13 Si2 to facilitate standardization of common power format
Cadence and the Silicon Integration Initiative have agreed on Si2 facilitating standardization of the Common Power Format through the IEEE.
2009-07-28 Power to take center stage at DAC
Power, arguably today's No. 1 headache for designers, will be the theme of workshops, tutorials, meetings, presentations and technical tracks at the 46th Design Automation Conference (DAC
2006-10-16 Power standard standoff reaches stalemate
Participants behind two rival efforts to define a standard IC power description format are attempting to make their initiatives more inclusive
2009-03-19 Power management for optimal design
This article describes a holistic approach for managing and optimizing the power in a design. Effective power management involves proper understanding the application of a chip, technology selection, design techniques and methodology
2006-07-25 Power Forward Initiative invites EDA companies
The Power Forward Initiative announced its plan to invite a limited number of EDA companies to participate in the Initiative
2008-05-05 Power Forward Initiative gets MindTree onboard
MindTree has joined the Power Forward Initiative and will be offering a Common Power Format-enabled low-power flow to its design services customers.
2007-07-16 Multivoltage verification solution eases low-power design
MaVeric is a comprehensive multivoltage verification solution that hopes to ease designers' struggles with low-power designs that require the verification of multiple voltage "islands
2007-05-16 Low-power IC design kit enables representative design
The Low-Power Methodology Kit from Cadence Design Systems includes a wireless "representative design" implemented using multiple supply voltage and power shutoff methods
2007-03-23 Hope fades for IC power standards union
The hoped-for-convergence between two rival IC low-power specifications will not likely take place anytime soon
2007-05-01 Hope dims for power spec merger
Two rival specification formats for low-power IC design are now publicly available, and backers of both agree that it would be technically feasible to converge them into a single standard. But disagreements over how that convergence should take place threaten to block further progress
2012-08-08 Grasping power awareness in RTL design analysis
Find out how formats such as CPF and UPF play a key role in capturing power intent for RTL design analysis and verification
2008-05-30 Faraday, NemoChips develop low power mobile platform
Faraday Technology Corp. and NemoChip have partnered to develop next-generation low power mobile platform based on Cadence Low-Power Solution
2012-10-19 Employ hierarchical methods for power intent specification
Here's a guide to using a hierarchical low-power design methodology
2006-12-01 EDA vendor rivalry bogs single power spec
Amid calls for a single power spec throughout the design flow, EDA vendor rivalry continues to fuel two separate efforts to develop a low-power description standard
2006-09-18 EDA rivals spar over power issues
Any EDA vendor or large EDA user will tell you there's a compelling need for a standard way to express power-management intent throughout the IC design flow. The problem is that two separate groups are working toward that objective, amid profound disagreements over how to get there
2012-04-30 Design for power methodology: From architectural plan to signoff
Here's a look at a holistic design for power methodology that spans from architectural decisions through front-end design to physical implementation and sign-off
2007-03-16 CPF-compliant tools aim for low power
Cadence Design Systems Inc. has added the Common Power Format to its existing logic design, verification and implementation tools.
2007-04-25 Common Platform partners deliver 65nm reference flow
Cadence Design Systems Inc. announced the immediate availability of the 65nm Common Power Format (CPF) enabled reference flow targeting the Common Platform technology.
2006-10-06 Coalition seeks to unify IC power standards efforts
The Silicon Integration Initiative launched the Low Power Coalition which may help unite two disparate efforts for standardizing a power specification format
2006-11-06 Cadence, Si2 team up for unified low-power standard
Cadence and Silicon Integration Initiative partnered to enable a common industry standard for low-power design, implementation and verificationthe Common Power Format.
2006-05-23 Cadence, others form power initiative
Cadence has announced the formation of the Power Forward Initiative, which aims to address obstacles to lower-power IC design that face the electronics industry
2007-02-01 Cadence deploys CPF in low-power design flow
Cadence Design Systems has added the Common Power Format (CPF) to its existing logic design, verification and implementation tools.
2013-01-02 Apply formal methods to power-aware verification
Read about an apps approach for implementing formal methods to power-aware verification
2007-06-18 Advanced low-power modes stump IC designers
While EDA vendors are still fighting over two low-power formats, a larger problem may have been obscured: Low-power techniques are so difficult that a rethinking of the entire IC design flow may be needed
2011-01-20 32/28-nm reference flow for Common Platform Alliance ushered
Cadence's 32/28nm Low-Power RTL-to-GDSII Silicon Realization Reference features new design intent, abstraction and convergence capabilities giving more deterministic path to advanced silicon
2009-02-13 What's in store for P1801 (Unified Power Format
A common industry standard for low power design and verification will satisfy what customers have needed all along
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