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2005-11-08 Rowley rolls development tools for Dallas Semi's MAXQ MCUs
Dallas Semiconductor announced the availability of the embedded development tools for the MAXQ 16-bit RISC family of MCUs.
2007-02-05 Rewriting flash memory in user program mode using asynchronous serial communication
This article describes how data to be rewritten in the flash memory on the master side is written to the flash memory on the slave side, and how data to be rewritten is transferred using asynchronous serial communication.
2005-11-30 Reducing code size without sacrificing performance
Through an iterative process of building application code using different compiler optimization options and profiling the result, developers can hone in and identify infrequently used and non-critical sections of code to trade off performance where it matters least for reduced code size, providing minimal impact on system performance.
2001-05-01 Reconfiguring SoC according to Garp
Programmable SoC components, containing a microcontroller and reconfigurable hardware, promise the flexibility of software and the performance of hardware.
2003-06-16 Reconfigurable computing driving new era for DSP
A new computing paradigm for DSP applications that retains the inherent programmability of a software-driven solution while also achieving the raw processing speed and low power consumption of a hardware solution is needed to support the DSP industry's growth.
2004-01-14 Quadros RTOS supports IAR C/C++ development tool
Quadros Systems and IAR Systems have released a port of the RTXC Quadros RTOS for the IAR Systems ARM Embedded Workbench along with an RTOS-aware plug-in.
2002-08-29 Prolific joins Synopsys in-Sync, TAP-in programs
Prolific Inc. has joined the Synopsys in-Sync and TAP-in programs to ensure interoperability of its ProLiquid software with Synopsys' PrimeTime and Library Compiler tools, and the Liberty modeling format.
2000-11-29 Programming the Siemens C167CR CAN interface: A real life case (Constructing the hardware)
This application note provides a set of procedures on how to connect two Keil single-board computers together to construct a working two-node CAN network. It discusses the instructions on loading and using the Keil monitor and debugger to operate and evaluate the entire system.
2000-11-29 Programming the Siemens C167CR CAN interface: A real life case
This application note demonstrates programming the on-chip CAN interface of the Siemens C167CR microcontroller using the Keil C166 C Compiler and two Keil MCB167 evaluation boards.
2003-10-09 Process tool promises yield optimization
PDF Solutions Inc. is expanding into EDA with a tool that claims to improve designs for optimum yield during the physical-synthesis stage.
2013-09-17 Port classic CodeWarrior project to newer version
Know the proper steps to manually port a legacy CodeWarrior project developed using a classic CodeWarrior product into the current Eclipse-based CodeWarrior for Microcontroller v10.4.
2003-03-19 Philips' Silicon Hive to develop IP cores
Philips Research is spinning out a reconfigurable computing architecture it has kept under wraps since the early 1990s to an incubator company called Silicon Hive, which will develop and license synthesizable IP cores.
2005-04-04 PGI expands cross-platform support
The Portland Group released v6.0 of its PGI Workstation-class of Fortran, C and C++ compilers and development tools.
2005-02-09 Patriot Scientific upgrades development tools
Patriot Scientific announced that it has completed a major upgrade to its development tools.
2003-10-21 Panelists, keynoter cite EDA interoperability roadblocks
Panelists explored EDA interoperability "hot buttons" at the Synopsys EDA Interoperability Developer's Forum held last October 16-17.
2003-07-01 Optimizing image processing algorithms for FPGAs
A high-level algorithmic programming language can be mapped into FPGAs by modifying C and creating SA-C.
2007-04-16 Optimize compilers and embedded DSP software
Understanding the workings of the DSP architecture, compiler, and the application algorithms can speed up applications, sometimes by an order of magnitude. This article will summarize some of the techniques that can improve the performance of your code in terms of cycle count, memory use, and power consumption.
2006-10-02 Optimize C programs for embedded SOC apps
This article discusses how C programmers for embedded processor cores within SoCs can reduce both code-execution time and memory footprint.
2004-04-29 Nvidia GPU designed with Synopsys platform
Synopsys has announced that Nvidia's new GeForce 6800 graphics processing unit was designed with Synopsys' Galaxy Design Platform.
2006-04-27 Nvidia adopts Synopsys' topographical tech
Synopsys announced that Nvidia is deploying the "topographical technology" in Synopsys' Design Compiler Ultra.
2007-08-20 Novelics unveils high-performance memory compilers
Novelics has launched the Web-based MemQuest memory compiler platform allows SoC designers to explore their entire embedded memory subsystem.
2011-05-09 Next-gen virtual machine tech ideal for live app analysis
Atego has rolled out the Aonix Perc Ultra 6, its latest version of embedded virtual machine technology that features Java 6 language compatibility and a graphical console for live application analysis.
2005-03-11 New TASKING M16C version available
A new version of Altium's TASKING M16C software development toolset was released, which the company claims to excel in performance of generated code and accelerates application development.
2011-05-10 New ARM SDKs launched
ARM releases version 5.0 of the ARM Compiler, as well as the ARM DS-5 Professional Edition for ARM processor-based ASICs and ASSP devices.
2006-06-08 MQX RTOS includes debugging solution
MQX Embedded and iSYSTEM AG announced that the winIDEA software has been adapted to provide an integrated debugging solution.
2002-01-16 MIPS scores software support for its processors
Both Microsoft Corp. and Metrowerks Inc. announced this week that their software products would support the MIPS microprocessors of MIPS Technologies Inc.
2006-06-29 Micronas tapes-out HDTV chip with Synopsys solution
Synopsys announced that Micronas has taped-out one of its HDTV chips using Synopsys' IC Compiler physical implementation solution.
2000-11-29 Memory models in C16x
This application note discusses memory models for Keil's C16x C Compiler. The memory models will be utilized to group together data objects and will determine the use of a segmented or a non-segmented function call.
2001-04-23 Memories
This application note discusses the process of selection and use of embedded memories available for designing digital ASICs at AMI. It also describes the memory compiler tool and the memory synthesizer tool.
2001-05-15 Loop partitioning on the TMS320C6x
This application note describes the process used to develop loop partitioning for Texas Instruments' TMS320C6x DSP family.
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