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2007-01-24 Mosaid touts first 65nm memory controller IP
Mosaid Technologies announced what it called the industry's first complete DDR SDRAM controller and interface IP, as well as fractional PLL IP, in 65nm process technology
2006-04-12 RISC processor integrates display controller
Toshiba announced the availability of the TX4961XBG-240, a 64bit RISC processor with integrated graphics and display controller
2006-11-01 VoIP chip loaded with GbE devices
Texas Instruments Inc.'s latest VoIP processor ensures delay-free voice in small- and medium-business applications. The TNETV1051 combines a 300MHz MIPS processor and 150MHz C55x DSP with dual GbE medium-access control (MAC) devices and an on-chip GbE switch
2006-09-15 VoIP chip from TI loads GbE support
TI's TNETV1051 VoIP device combines a 300MHz MIPS processor and 150MHz C55x DSP with dual GbE MAC devices and an on-chip Gbe switch
2002-05-02 NEC adds L2 cache, DRAM controller to Vr processor
NEC Corp. has taken the wraps off a MIPS-based 64-bit embedded processor that integrates Level 2 cache and a DRAM controller, both equipped with error-correction coding features
2005-08-12 Mosaid, UMC, team on DRAM controller IP
Foundry United Microelectronics Corp. is working with Mosaid Technologies Inc. to develop Double Data Rate and DDR2 synchronous DRAM memory controller intellectual property core for use with or UMC's 90nm and 130nm manufacturing process, Mosaid said
2008-04-17 LCD processors include touchscreen controller
Freescale has released ColdFire LCD microprocessors with an integrated touch-screen controller to help accelerate deployment of touch-based control in industrial human-machine interface applications
2008-08-18 DDR IP solutions speed up SoC design operation
Synopsys has introduced a full range of silicon- proven DesignWare DDR IP solutions for SoCs that need an interface to high-performance DDR3, DDR2 and DDR memory subsystems
2014-11-17 Characterisation of DDR memory system margins
Memories are vital to system operation and performance. Designers need a better way to look inside the memory sub-system to ensure the system is optimised for production.
2004-05-12 Rambus offers interface IP for DDR, DDR2 DRAMs
Rambus for the first time is offering interface intellectual property for industry-standard double-data-rate, DDR2 and XDR DRAMs.
2011-07-04 Step-down regulator targets SDRAM controllers
The dual-channel monolithic synchronous step-down regulator launched by Linear is specifically designed for DDR1, DDR2 and DDR3 SDRAM controllers
2002-07-05 Broadcom security chip speeds SSL/TLS record processing
A Broadcom Corp. security processor chip, the BCM5850, is a 2.4Gbps device, speeds the throughput of SSL and TLS e-commerce transactions and data transfers, avoiding security-related bottlenecks on high-speed networks
2007-06-01 System LSI chips tailored for STBs with hard drives
NEC Electronics today introduced two new additions to its acclaimed EMMA lineup of system LSI chips for digital AV devices.
2005-03-21 ST MCU packs a lot of features
STMicroelectronics announced details of a new multi-purpose microcontroller that targets applications in wireless infrastructure equipment.
2004-07-26 Renesas MCP incorporates CPU core, PCIC
Renesas developed a 32-bit microprocessor that incorporates the SH-4A and a PCI bus controller
2008-06-02 Midsize motherboards branch out
New product introductions of the past six months show how fragmented the market is for embedded motherboards and single-board computers, particularly when it comes to small formats. In the midsize realm, ranging from about 40-50-inch2, however, the activity centers primarily on 6.7-inch x 6.7-inch Mini-ITX and 5.75-inch x 8-inch EBX motherboards, though the boards themselves are diverse.
2004-12-07 Fast multi-media platform fits 3.5-in. HDD form-factor
Evalue announced a 3.5-inch single computer board providing GHz high speed and versatile multimedia platform for the embedded apps.
2002-06-13 Denali launches IP core for optimized memory access
Denali Software Inc., a provider of memory system designs, has launched Databahn core for SoC bandwidth allocation.
2009-06-09 IP-verified DDR3 runs at 1600Mbit/s
Synopsys Inc. has announced that its DesignWare DDR3/2 PHY and digital controller IP is the first DDR3 IP that has been fully verified in test silicon at 1600Mbit/s, the maximum data-rate of the JEDEC DDR3 specification
2015-07-08 Implementing JTAG boundary scan
Boundary scan, based on the IEEE 1149.x set of standards, is the structural testing of PCBs and their installed components. Here are case studies on the implementation of this test.
2007-12-20 Sony base station streams media content anytime, anywhere
The $250 Sony LF-V30 is 4G in the LocationFree line and adds Wi-Fi connectivity to Ethernet in its network interface.
2002-07-26 Motorola ships processor using new SoC architecture
Motorola's MPC8560 integrated communications processor uses the PowerQUICC III SoC architecture to provide improved control processing and forwarding plane bandwidth.
2005-03-21 MPU boasts enhanced performance
TAEC's new 64bit single-chip MIPS-based RISC microprocessor is targeted at diverse digital consumer apps, including IP STB, home gateways and multimedia appliances
2002-01-18 VIA chipset supports Athlon XP processors
Featuring 4Gb DDR SDRAM support and an 8x AGP, the ProSavageDDR KM266 is specifically designed for AMD Athlon processor-based PCs running Windows XP OS and applications
2002-11-25 IDT boosts bandwidth of communications processor
IDT has debuted its RC32438 integrated communications processor that incorporate a 32-bit MIPS CPU core with a DDR memory controller, which provides a higher memory bandwidth compared to an SDRAM-based solution
2007-11-09 DRAM makers ready for DDR3 demand surge
Major players in the memory sector are gearing up to supply the electronics industry when demand for DDR3 SDRAM kicks in next year
2007-05-14 DDR2 IP and configurability
The process of creating a PHY for a specific design is unique to every chip. The planning process traditionally starts with the pad frame design, although designs for the package and even the PCB can precede it
2007-04-16 Using logic-optimized FPGAs in displays
Image quality in FPDs is highly subjective, and image-enhancement algorithm specifications continue to evolve. As a result, low-cost, logic-optimized FPGAs and reference designs enable designers to modify image-enhancement algorithms quickly and easily.
2004-04-30 Freescale updates PowerQuicc families
Freescale Semiconductor announced updates of its PowerQuicc II Pro and PowerQuicc III families at the Smart Network Developers Forum.
2005-10-03 Choice for Zigbee PAN coordinator
Learn the key requirements for a PAN coordinator as it manages an entire Zigbee network.
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