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2014-11-17 Characterisation of DDR memory system margins
Memories are vital to system operation and performance. Designers need a better way to look inside the memory sub-system to ensure the system is optimised for production
2006-07-27 ARM releases next-gen DDR memory solutions
The new ARM Velocity DDR products are compliant with JEDEC standards for DDR, DDR2, Mobile DDR and GDDR3 SDRAM and support standard CMOS processes on 130-, 110-, 90- and 65nm nodes for leading foundries
2009-01-15 ZIF probe tips handle DDR, GDDR validation
Agilent Technologies and Hynix Semiconductor have developed a high-bandwidth, high-performance long-wire ZIF probe tip optimized for DDR and GDDR SDRAM validation
2005-07-20 WEDC rolls new DDR SDRAM
WEDC's new 512MB DDR SDRAM consists of sixteen 32M x 84 banks DDR SDRAMs in FBGA packages mounted on a 200-pin FR4 substrate
2004-04-20 WED module targets memory system apps
The 2GB DDR SDRAM registered ECC memory module from White Electronic Designs is claimed by the company to provide maximum performance for memory system apps.
2005-08-01 Virtual system 'platform' rolls
Carbon Design moves from point tools to integrated platforms with its new virtual system prototyping product
2007-01-26 Virtex-4-based devt platform speeds embedded system designs
Xilinx has announced immediate availability of the Pb-free, RoHS-compliant ML410 development platform based on the Virtex-4 FX60 FPGA.
2015-05-11 Verilog-AMS vs SPICE view for DDR, LCD verification
In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories
2007-07-13 V58C2256(804/404/164)SC high performance 256Mbit DDR SDRAM
The V58C2256(804/404/164)SC is a four bank DDR DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x 4Mbit x 16 (164) or 4 banks x 16Mbit x 4 (404
2007-07-23 V58C2128x SB high performance 128Mbit DDR SDRAM
Promos technolgies' V58C2128(804/404/164)SB achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock
2008-05-26 Using the FullFlex dual-port DDR interface
Cypress Semiconductor's FullFlex Dual-Port offers DDR mode to achieve the same data bandwidth of an SDR interface with half of the data pins, or twice the data bandwidth with the same amount of pins
2009-02-09 Using high-performance DDR, DDR2, and DDR3 SDRAM with SOPC Builder
The Altera DDR, DDR2, and DDR3 SDRAM high-performance controller MegaCore functions version 7.1 and later support SOPC Builder
2008-06-23 Understanding TI's PCB routing rule-based DDR timing specification
This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious.
2007-01-30 Tundra PowerPC host bridge cuts system cost
Tundra's Tsi110 host bridge offers an optimized performance/power solution when designed in conjunction with lower frequency, lower power PowerPC processors.
2002-10-01 TI samples DDR-II logic register for memory evaluation
Texas Instruments is sampling the SN74SSTU32864 25-bit configurable registered buffer for evaluation in DDR-II memory apps
2009-01-29 The bad stuff impacting DDR timing budgets and ways to avoid 'em
Why bother with a DDR "PHY" when some SSTL I/O's with potentially a DLL or PLL slapped together with glue logic will do the trick of interfacing to an SDRAM
2007-11-12 Test system targets multiple memory MCP devices
A high-speed, high-throughput memory test system for MCPs has been introduced by Advantest Corp
2003-08-14 Teradyne test system to be deployed by ULi
Teradyne has announced that ULi Electronics, a developer of core logic chipsets and related host-based peripherals, has selected its Tiger test system as the characterization and production solution for their Northbridge and Southbridge PC chips
2007-06-01 System LSI chips tailored for STBs with hard drives
NEC Electronics today introduced two new additions to its acclaimed EMMA lineup of system LSI chips for digital AV devices
2015-02-12 Synopsys rolls out DDR Explorer for memory sub-systems
Using DDR Explorer, designers can analyse their DDR memory sub-system and optimise their architecture to increase efficiency by up to 20 per cent, while achieving 10 times faster turnaround time.
2007-09-17 Simplify DDR validation with SI methods
As DDR memory technology evolves, DDR signal integrity becomes more challenginghence, it is essential to use a proper probing method to obtain the best result
2001-04-15 Same-die tactic eases DDR transition
The industry consensus is clear: DDR's time has come. Now what design issues must engineers consider, and what can DRAM suppliers do to make this memory transition happen smoothly and seamlessly
2007-04-02 Reference system: MCH OPB DDR SDRAM with OPB Central DMA
This application note describes how to set up MicroBlaze parameters for caching, the clocking structure for the MCH OPB DDR SDRAM, and parameters for OPB burst transactions from the OPB Central DMA controller. This reference system is targeted for the Xilinx SP305 Spartan-3 development board.
2004-05-12 Rambus offers interface IP for DDR, DDR2 DRAMs
Rambus for the first time is offering interface intellectual property for industry-standard double-data-rate, DDR2 and XDR DRAMs.
2006-11-13 Qimonda intros 183MHz DDR Mobile-RAM
Qimonda AG has launched its 183MHz DDR synchronous Mobile-RAM offering a capacity of 512Mbit in a 60-ball FBGA package with 1.8V power supply
2007-06-01 Prius drives with smart GPS navigation system
A DVD player under the driver's seat holds navigation system map data that's read in conjunction with the real-time GPS satellite location to yield the guidance information displayed the Toyota Prius dashboard screen
2010-04-13 Power controller handles DDR memories
Exar Corp. has extended its line of low-voltage, step-down controllers specifically targeted at DDR memory power architectures
2008-12-01 Nüvi 205 expands horizon for GPS navigation system
No longer at prices that force PNDs into locked glass cabinets, the $199 PND is driving the growing commodity status of standalone GPS systems.
2009-06-05 NVRAM system achieves up to 200MBps peak transfer
AgigA Tech Inc. has unveiled what it claims is the first high-speed, high-density non-volatile RAM system dubbed AGIGARAM
2004-11-19 New IP core simplifies overall system design
Actel announced a new IP core optimized for its FPGAs that provides a high-performance, synchronous interface to double data rate SDRAM memories.
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