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What is DDR memory?
Double Data Rate is a type of memory IC used in computers. Memory or storage medium is a device that where data can be held. DDR SDRAM (synchronous dynamic random access memory) is a type of memory widely used in computers.
total search956 articles
2009-01-15 ZIF probe tips handle DDR, GDDR validation
Agilent Technologies and Hynix Semiconductor have developed a high-bandwidth, high-performance long-wire ZIF probe tip optimized for DDR and GDDR SDRAM validation.
2014-11-14 Worst practices for DDR memory testing
There are some things to watch out for when testing DDR memory deviceswe call them worst practices. These can adversely influence measurement accuracy or even wreck your probing setup.
2005-07-20 WEDC rolls new DDR SDRAM
WEDC's new 512MB DDR SDRAM consists of sixteen 32M x 84 banks DDR SDRAMs in FBGA packages mounted on a 200-pin FR4 substrate.
2004-08-17 WEDC DDR SDRAMs offer wide variety of densities, heights
WEDC has developed a complete family of Double Data Rate SDRAM modules that target desktop PCs, notebooks, and compact and sub-compact computers.
2002-08-01 WEDC DDR SDRAM occupies less board space
White Electronic Designs has released 128MB DDR SDRAM MCPs that are designed to complement high performance memory controllers.
2002-01-29 VIA launches DDR chipset for mobile Pentium III
The ProSavageDDR PN266T is claimed to be the first mobile chipset to support fast DDR266 memory for the mobile Pentium III processor.
2015-05-11 Verilog-AMS vs SPICE view for DDR, LCD verification
In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories.
2007-07-13 V58C2256(804/404/164)SC high performance 256Mbit DDR SDRAM
The V58C2256(804/404/164)SC is a four bank DDR DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x 4Mbit x 16 (164) or 4 banks x 16Mbit x 4 (404).
2007-07-23 V58C2128x SB high performance 128Mbit DDR SDRAM
Promos technolgies' V58C2128(804/404/164)SB achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
2008-05-26 Using the FullFlex dual-port DDR interface
Cypress Semiconductor's FullFlex Dual-Port offers DDR mode to achieve the same data bandwidth of an SDR interface with half of the data pins, or twice the data bandwidth with the same amount of pins.
2014-11-03 Using interposers for DDR memory testing
So, say you need to get probes onto a dual data-rate memory device and some (or all) of the pins are inaccessible. Here is where chip interposers come in.
2009-02-09 Using high-performance DDR, DDR2, and DDR3 SDRAM with SOPC Builder
The Altera DDR, DDR2, and DDR3 SDRAM high-performance controller MegaCore functions version 7.1 and later support SOPC Builder.
2002-01-17 Unitech Electronics motherboard supports DDR 333 memories
The 645 ULTRA computer motherboard integrates an SiS645 chipset, allowing for DDR 333 support.
2008-06-23 Understanding TI's PCB routing rule-based DDR timing specification
This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious.
2006-08-25 TI's PCIe x1 PHY supports source synchronous, DDR clocking
TI's new PCIe x1 PHY chip supports source synchronous clocking and DDR clocking, easing board layout design and enabling customers to choose low-cost FPGAs that don't run faster than 125MHz.
2002-10-01 TI samples DDR-II logic register for memory evaluation
Texas Instruments is sampling the SN74SSTU32864 25-bit configurable registered buffer for evaluation in DDR-II memory apps.
2009-01-29 The bad stuff impacting DDR timing budgets and ways to avoid 'em
Why bother with a DDR "PHY" when some SSTL I/O's with potentially a DLL or PLL slapped together with glue logic will do the trick of interfacing to an SDRAM?
2006-11-07 Temperature sensor targets DDR memory modules
Maxim Integrated Products has introduced a small and low-cost temperature sensor designed for thermal monitoring in DDR memory modules.
2007-03-12 Synthesizable CIO DDR RLDRAM II controller for Virtex-4 FPGAs
This application note describes how to use a Virtex-4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 200/235MHz with data transfers at 400/470Mbps per pin.
2004-12-09 Synthesizable 400Mbps DDR SDRAM controller
This app note explains how to use a Virtex-II device to interface to a DDR SDRAM device.
2001-04-12 Synthesizable 1.6GBps DDR SDRAM controller
This application note describes a 100MHz synthesizable reference controller design for a 64-bit DDR SDRAM.
2015-02-12 Synopsys rolls out DDR Explorer for memory sub-systems
Using DDR Explorer, designers can analyse their DDR memory sub-system and optimise their architecture to increase efficiency by up to 20 per cent, while achieving 10 times faster turnaround time.
2001-07-02 Solving The Memory Bottleneck - DDR And Its Enabling Chipset
This paper describes the numerous benefits of DDR (double data rate) memory in improving bandwidth bottlenecks for many PC applications.
2002-03-19 SiS chipset supports 400MHz DDR memory
Silicon Integrated Systems claims bragging rights with its introduction of what it called the first chipset able to support 400MHz DDR DRAMs.
2007-09-17 Simplify DDR validation with SI methods
As DDR memory technology evolves, DDR signal integrity becomes more challenginghence, it is essential to use a proper probing method to obtain the best result.
2006-07-07 SDRAM-DDR memory unit touts multichip plastic packaging
Austin Semiconductor has launched its 1.2Gbit, SDRAM-DDR memory family in a 219-pin BGA.
2003-01-24 Samsung ships 4GB DDR DIMM
Samsung Electronics Co, Ltd. has announced the release of the industry's first 4GB DDR DIMM for use in high-performance apps.
2001-04-15 Same-die tactic eases DDR transition
The industry consensus is clear: DDR's time has come. Now what design issues must engineers consider, and what can DRAM suppliers do to make this memory transition happen smoothly and seamlessly?
2007-07-24 Regulators up power efficiency in DDR apps by 93%
Freescale Semiconductor has introduced a series of single- and dual-power regulator ICs that provide efficient power management for DDR applications.
2007-04-02 Reference system: MCH OPB DDR SDRAM with OPB Central DMA
This application note describes how to set up MicroBlaze parameters for caching, the clocking structure for the MCH OPB DDR SDRAM, and parameters for OPB burst transactions from the OPB Central DMA controller. This reference system is targeted for the Xilinx SP305 Spartan-3 development board.
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