Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > DFM techniques

DFM techniques Search results

?
?
total search52 articles
2006-09-01 Restricted design rules challenge DFM
The recent Design Automation Conference made it clear that the EDA industry is counting on DFM for a much-needed boost. But the RDRs that are quietly emerging for 45nm and smaller geometries may reduce the need for some DFM tools and techniques, some observers say.
2007-03-16 Electrical DFM promises gains in parametric yield
Design techniques are under greater pressure to provide equivalent scaling to enable the semiconductor road map to continue in a cost-effective way
2007-03-16 DFM demands holistic approach
The infrastructure required to make trade-offs among the different techniques and determine the optimal approach should be one where the actual software takes into account the implications of other DFM issues. The idea is to create a holistic approach to DFM for the design and analysis flow.
2005-05-11 TSMC expands DFM recommendations at 90nm
Taiwan Semiconductor Mfg Co. Ltd is expanding its design-for-manufacturing recommendations for engineers working with 90nm design rules, company managers told the TSMC 2005 Technology Symposium here last week.
2006-07-26 TSMC adds support for Blaze DFM optimization software
Taiwan Semiconductor Manufacturing Co. Ltd is adding support for Blaze MO optimization software from Blaze DFM Inc. with both companies supplying evaluation kits
2004-09-17 Synopsys, Photronics form DFM collaboration
EDA software vendor Synopsys Inc. and Photronics, a photomask company, have formed a collaborative program intended to improve the manufacturability and quality of advanced photomasks and reduce design-to-photomask cycle times, Synopsys said.
2004-09-01 Synopsys CEO calls for DFM cooperation
Synopsys CEO called on the design and fab communities to develop
2005-06-29 Innovation, cooperation key to overcoming DFM issues, says Synopsys exec
Speaking to an audience of mostly photomask manufacturing executives at the Advanced Reticle Symposium Tuesday (June 28), Synopsys Inc.'s Michel Cote praised the way the EDA industry has responded to design-for-manufacturing (DFM) challenges with innovation and said continued industry cooperation is the key to overcoming them
2006-01-24 EDA partnership yields DFM sign-off tool
Nannor Technologies Inc. and Predictions Software announced the integration of the Acuma chip level layout optimization tool and the EYES yield analysis software.
2006-11-28 Clear Shape solution promises fast DFM hotspot detection
Clear Shape Technologies has announced InShape, said to be the first model-based full-chip Design Manufacturability Checker that predicts accurate silicon shapes, providing designers the ability to do fast, accurate DFM hotspot detection of catastrophic failures
2008-03-17 Bring DFM/DFY into the routing engine
In reality, DFM/DFY tools need to use a mixture of rules- and model-based techniques as appropriate. The solution is to bring DFM/DFY upstream into the design process; to create a design that is correct by construction; and to hand-off a design that is as manufacturing- and yield-friendly as possible.
2006-11-16 DFM too complex,' experts say
Speakers told the Bacus Photomask Technology Symposium that DFM technology is too complex and suggested the use of standardized layout elements, library cells or an "integrated" DFM methodology
2008-06-12 TSMC targets to unify 32nm design flow
Facing the 32nm challenge, Taiwan Semiconductor Manufacturing Co. Ltd is putting the pedal to the metal with a new design-for-manufacturing scheme.
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node.
2005-06-13 TSMC releases reference design flow for 65nm processes
Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes.
2008-03-17 Succeed at 65nm design
A true DFM-aware environment accounts for process variability and lithographic effects in the context of timing, power, noise and yield at every stage of the flow. This begins with the characterization of the cell library, continues through implementation, analysis and optimization, and ends with sign-off verification
2006-10-02 Self-healing chips prevent system failure
Semiconductor Research Corp. and the National Science Foundation are funding a groundbreaking research effort into "self-healing" chips that can detect and repair defects in the field.
2009-03-24 Process variability gets a second chance
Mentor Graphics Corp. has a new message: process variability is not all bad. In fact, it could be considered a competitive advantage if properly dealt with, according to executives at the firm.
2013-06-06 Parasitic extraction in the double-patterning age
Determining the impact of double-patterning on electrical sign-off can be better achieved by understanding how PEX tools have evolved to handle this challenge.
2005-12-01 Manufacturing moves into design flow
null
2008-08-01 Looking beyond advanced design geometries
With the presence of the design geometries between 1000nm and 1nm, we can start deploying 32nm flows and find the solutions of the transitional barriers between 32nm and 22nm. Design verification plays a vital role in reducing the design cost and improving the yield of the new products and product platforms.
2006-07-20 Design forum is heavy on ESL this year
The Design Automation Conference next week in San Francisco, California comes with a program heavy on ESL and embedded systems design, design-for-manufacturability, power-aware design and verification. See the details inside.
2005-01-06 China to invest more in 0.18?m technology
Chinese fabs have a unique opportunity to invest more in 0.18?m technology, leveraging with the best EDA technologies that are now available.
2008-03-18 Synopsys, SMIC tip 90nm reference design flow
Synopsys Inc. and SMIC have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test and DFM capabilities
2009-03-19 Power management for optimal design
This article describes a holistic approach for managing and optimizing the power in a design. Effective power management involves proper understanding the application of a chip, technology selection, design techniques and methodology
2007-08-01 Follow a balanced DFx flow
The best DFx flow available today combines the DFM-aware features in today's synthesis, placement and routing solutions with a post-route (pre-GDS) interconnect optimization step
2006-09-18 Leakage takes priority at 65nm
As the first reports on 65nm design come in, the good news is that there seems to be no problems at 65nm that weren't present at 90nm. The bad news is that some of the problems that plagued 90nm get much worse at the new node.
2012-06-04 Globalfoundries to demo enhanced silicon-validated design flow
According to the company, the flow provides proven and complete front-to-back support for advanced analog/mixed-signal (AMS) design using the industry's latest design automation technology.
2005-04-18 DATE minds offer an array of fixes for SoC design
Designing high-performance SoCs needs a breakthrough from system-level design through manufacturing, according to DATE.
2005-06-23 Annual ARS focuses on impact of semiconductor worldwide
In view of the 40th anniversary of Moore's law, the 11th annual Advanced Reticle Symposium (ARS) will address the state of semiconductor technology advancement and its impact not only on economic growth but also on society worldwide.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top