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DFM tools for 45nm Search results

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2006-10-31 Synopsys unveils DFM tools for 45nm, beyond
Synopsys has unveiled a new family of process-aware DFM products that analyze variability effects at the custom/analog design stage for 45nm and smaller designs
2007-03-16 DFM demands holistic approach
The infrastructure required to make trade-offs among the different techniques and determine the optimal approach should be one where the actual software takes into account the implications of other DFM issues. The idea is to create a holistic approach to DFM for the design and analysis flow
2005-06-09 TI sticks with Synopsys for 65nm, 45nm nodes
Texas Instruments Inc. has decided to extend its use of design-for-manufacturing EDA tools from Synopsys Inc. to the 65nm manufacturing process node and has selected two Synopsys technology CAD tools for use at the 45nm node, Synopsys said
2008-03-20 Synopsys IC Compiler qualifies for TSMC 45nm process
Synopsys has announced the qualification and immediate availability of its IC Compiler for designs targeting TSMC's 45nm process
2005-10-07 Speaker calls for mask design rule standard
A proliferation of mask design rules from different sources calls out for a standard
2006-09-01 Restricted design rules challenge DFM
The recent Design Automation Conference made it clear that the EDA industry is counting on DFM for a much-needed boost. But the RDRs that are quietly emerging for 45nm and smaller geometries may reduce the need for some DFM tools and techniques, some observers say.
2007-06-01 IC designers favor less complex DFM
During the IEEE Electronic Design Process workshop, IC design experts point out that current approaches to design-for-manufacturing (DFM) may be yielding too little for the amount of effort and cost involved
2006-10-18 IC design tool touts process-aware DFM
Synopsys two "process-aware" tools that help custom- and analog-IC designers analyze the impact of transistor variability on circuit layouts
2007-03-16 Electrical DFM promises gains in parametric yield
Design techniques are under greater pressure to provide equivalent scaling to enable the semiconductor road map to continue in a cost-effective way.
2006-04-03 Easier OPC is tools' promise
Aprio Technologies and Brion Technologies recently launched optical proximity correction tools that promise greater accuracy and flexible user controllability
2007-07-16 TSMC pulls curtains off 45nm design process
Taiwan Semiconductor Manufacturing Co. Ltd unveiled its latest and most ambitious design methodology for IC production at the challenging 45nm node
2007-02-01 Startup weaves new foundation for chip design
Fabbrix claims it can provide the regular circuit patterns or 'fabrics' needed by manufacturable designs at 65nm and belowwithout area, performance or power penalties.
2005-11-08 Panelists ponder challenges of 45nm
The move to the 45nm process node will be costly and challenging, but worth it for selected applications, according to panelists at the EDA Tech Forum here Thursday (Nov. 3
2004-09-23 Magma panelists explore whether DFM is the real deal
After much bravado, EDA vendors like Magma Design Automation and Mentor Graphics are starting to deliver viable design-for-manufacturability tools, or DFM-savvy tools
2007-06-18 Industry tackles approach to DFM, DFY issues
Experts from chip, EDA and foundry companies ask whether it's better to deal with DFM and DFY issues at tape-out or minister to the design starting at the register transfer level
2006-10-04 Industry players meet to discuss standard for Open DFM
Participants of the Open DFM Model Workshop last week explored issues ranging from DFM flows to encryption and identified possible next steps
2008-01-25 45nm: What Intel didn't tell you
Some high points of Intel's 45nm HKMG technology are: high-k first, metal-gate-last integration; hafnium oxide (HfO2) gate dielectric (1nm EOT); and dual band-edge work function metal gates (TiN for PMOS; TiAlN for NMOS). The gate-last integration is one point that needs a bit of clarification in the Intel process flow
2007-11-01 Addressing the issues of process node transition
To minimize some of the issues at 45nm designs, a heightened effort is required to develop tools and methodology to meet process power/performance and area entitlement from node to node
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node
2007-01-04 EDA to remain strong in 2007
The EDA should have another good year in store, according to executives from large and small EDA companies.
2007-02-16 EDA growth to continue this year
The EDA industry grew faster than expected in 2006 and is up for another good year, thanks to a healthy IC industry, an insatiable CE market and a move to 65nm and 45nm technologies
2006-10-02 Self-healing chips prevent system failure
Semiconductor Research Corp. and the National Science Foundation are funding a groundbreaking research effort into "self-healing" chips that can detect and repair defects in the field.
2008-08-26 Despite Q2 loss, Mentor remains positive
Mentor Graphics Corp. made a loss of $17.2 million on revenue of $182.4 million in Q2 ended July 31.
2007-11-01 Dealing with IP at 65nm and below
The demand for connectivity intellectual property (IP) for high-speed serial buses is increasing. High-speed serial buses require high-performance analog/mixed-signal circuits that can be designed using standard deep sub-micron CMOS technologies
2007-09-17 Asia's EDA moment is just around the corner
Mentor Graphics' Daniel Yang, managing director, Pacific Rim operations, discusses the Asian designer's future and how the region is shaping up to captivate the EDA industry.
2007-06-14 Rivals play down threat of Mentor's Sierra acquisition
Mentor Graphics' rivalsSynopsys, Cadence and Magma Designregard Mentor's Sierra acquisition as a minimal threat, and their own positions in 65/45nm IC design as strong
2005-06-01 OEMs to EDA world: Time to catch up
If the EDA industry provides tools on time, it will continue to be a growing market, says Dataquest analyst
2008-11-17 Fab tech roll call: survival of the fittest
Manufacturers are rolling out 45nm ICs, with 32nm designs in the works; 22nm and even smaller devices are in R&D. But delivery of chips at 32nm and beyond won't be a cool breeze
2007-06-25 Intel drafts inverse litho to cover EUV delay
With the possible delay of its EUV lithography, Intel disclosed it is developing a DFM technology that could extend optical scanners to the 22nm node
2005-12-28 IBM adopts Mentor's Calibre tech
Mentor Graphics announced that IBM has adopted the patent pending Calibre encryption technology for use with IBM's 90nm, 65nm and 45nm process design kits
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