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2009-03-20 Using the DLL Phase Offset Feature in Stratix II and HardCopy II Devices
This application note describes how to implement the delay-locked loop (DLL) phase offset feature with Altera's Stratix II and HardCopy II devices.
2003-06-19 Using the C8051Fxxx on-chip interface utilities DLL
The interface utilities DLL (dynamic link library) provides functions to download an Intel hex file to Flash and connect and disconnect to a C8051Fxxx microprocessor.
2009-08-28 LatticeSC sysCLOCK PLL/DLL user's guide
This user's guide describes the clocking resources available in the LatticeSC architecture.
2009-05-13 LatticeECP3 sysCLOCK PLL/DLL design and usage guide
This application note describes the clock resources available in the LatticeECP3 device architecture. Details are provided for primary clocks, secondary clocks and edge clocks as well as clock elements such as PLLs, DLLs, clock dividers and more.
2010-10-22 ZTE selects Cypress SRAMs for Ethernet switches
ZTE's new Ethernet switches feature 65nm 72-Mbit QDR II+ SRAM devices from Cypress
2004-12-01 Vector generation for structural testers
Sizing of modern ASICs and SoCs requires an array of vectors for comprehensive testing to achieve the required quality levels.
2000-06-26 Using the Virtex delay-locked loop
This application note demonstrates how to use the Virtex FPGA Series' four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits to implement several circuits that improve and simplify system-level design.
2006-12-08 True Circuits rolls out silicon proven 65nm analog IP
True Circuits Inc. has announced "silicon proven" phase-locked loop and delay-locked loop hard macros using TSMC's 65nm process.
2009-01-29 The bad stuff impacting DDR timing budgets and ways to avoid 'em
Why bother with a DDR "PHY" when some SSTL I/O's with potentially a DLL or PLL slapped together with glue logic will do the trick of interfacing to an SDRAM?
2004-01-01 Speeding up FPGA clock schemes
One of the most important steps in the design process is to identify how many different clocks to use and how to route them.
2001-04-15 Same-die tactic eases DDR transition
The industry consensus is clear: DDR's time has come. Now what design issues must engineers consider, and what can DRAM suppliers do to make this memory transition happen smoothly and seamlessly?
2003-12-16 PLLs, DLLs becoming reusable IP
PLLs and DLLs are becoming increasingly important in the SoC design and are gradually turning into IP that can actually be reused by ordinary mortals.
2004-02-02 Open architecture ATE tackles test woes
The basic idea behind the open architecture test system is to provide such modularization with specific focus on the use of third-party modules and test instruments.
2003-05-14 Infineon, Micron launch memory spec for comms, storage apps
Infineon Technologies AG and Micron Technology Inc. have come up with a complete specification for reduced latency DRAM II (RLDRAM II) architecture.
2007-01-01 Do timely testing to avoid cosmic ray damage
Modern memory devices exhibit significant and increasing sensitivity to radiation-induced errors. Accurate measurements and comparisons of radiation sensitivities of semiconductor memory devices require the control of test conditions commensurate with the complexity of the devices.
2010-05-25 Wrapper in Matlab for the STEVAL-MKI062V1
This application note provides information on the use of the API of the iNEMO software development kit (SDK), which provides easy-to-use function calls to obtain data from the sensors or to change settings.
2006-02-02 Wideband RF development platform records and plays back
Pentek's new development platforms are for realtime wideband data acquisition, signal processing and recording.
2013-05-07 Why DDR4 is not just a speed bump
The move to DDR4 incorporated changes to improve both speed and width, but there are other more significant changes.
2009-07-08 Watchdog board monitors app program, OS ops
ACCES I/O Products Inc. is offering a series of dedicated watchdog timer boards for PC/104-based embedded systems.
2008-07-18 Virage new DDR3 interface handles up to 1.6Gbit/s
Virage Logic has broadened its Intelli DDR memory interface product portfolio with the Intelli DDR3 memory interface that operates up to 1.6Gbit/s.
2015-04-14 Verifying ADAS in vehicles and in labs
Learn about the typical challenges that arise in verifying object data and testing the image processing algorithm. The XCP standard enables the necessary high data throughput in measurement and calibration.
2012-11-29 Using JESD204B for wideband data converter apps
The JESD204A/B interface minimises the number of digital inputs/outputs between data converters and other devices, such as FPGAs and SoCs.
2010-06-11 USB vendor commands with PSoC 3
This application note uses the Vendor class requests to communicate with and exercise PSoC 3.
2008-07-24 USB security dongle handles complicated access systems
Using a unique, hard-coded identification number, the USB-Key security device from Future Technology Devices International can interface to any USB host or hub to provide application software access control or as part of a more sophisticated key-based physical access control.
2006-07-12 USB module has 15 independent 16bit counter/timers
The new USB module from ACCES I/O Products features 15 independent 16bit counter/timers.
2005-12-06 USB box works as general-purpose hardware resource
Byte Paradigm's new GP-22050 BASE plug-and-play box can operate either as a bi-directional instrument or as a single-direction device. Each pin or signal can be individually defined as an input, an output or as a bi-directional line.
2010-11-04 Test dev software, PXI, FPGA products launched
Geotest updates ATEasy and launches new PXI digital & FGPA products.
2004-08-12 Synthesis suite targets unconventional designs
FTL's Merlin is a tool suite that includes behavioral synthesis from VHDL or SystemVerilog; analog synthesis from VHDL-AMS or Verilog-AMS; and analysis and simulation.
2004-10-01 Synthesis suite targets unconventional designs
FTL Systems is quietly preparing a complete IC design solution, but this small, privately held company isn't about to go head-to-head against the big EDA vendors.
2008-03-10 RLDRAM II clocking strategies
This technical note addresses the operation of the device outside the specified range of clock periods and the timing changes that occur in this mode of operation. It
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