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2015-08-20 Using DRC for SERDES PCB layouts
In order to be sure that SERDES bus traces on a routed printed circuit board are error free, you may use an automated design rule checker, which makes such tasks easier.
2001-05-28 Removing ERC and DRC error indicators
This application note describes how to remove ERC and DRC error indicators from an SCH or PCB drawing after the ERC or DRC report has been generated.
2003-05-07 GSI Lumonics acquires DRC division
GSI Lumonics Inc. has acquired the principal assets of the Encoder division of Dynamics Research Corp.
2006-07-18 DRC tool meets yield challenges of nanometer era
Mentor Graphics said its Calibre nmDRC tool redefines the traditional design rule checking (DRC) step to solve the yield challenges of the nanometer era.
2013-07-19 Address DRC debug issues in 20nm custom designs
Know the new debugging solutions that can help custom designers quickly and effectively achieve DRC closure on their advanced node designs.
2004-02-02 Write your own PCB design rule checker
After PCB design is captured in a schematic tool, a design rule checker (DRC) must be run to find any design rule violations. This must be done before backend processing starts.
2001-07-16 Validate EMC design rules with 3D simulation
This article provides an overview of EMC- and 3D-analysis tool capabilities that can enhance an your design's performance.
2013-02-12 UMC, Synopsys partner for design verification at 28nm
UMC selected Synopsys' IC Validator physical verification product for lithography hot-spot checking to accelerate physical signoff at 28nm.
2004-08-16 Timing closure: Hybrid optimization to the rescue
Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure.
2003-12-19 Tanner upgrades layout editor
Tanner EDA has released a new version of its L-Edit Pro Windows-based IC layout editor with new functionality and ease-of-use features.
2004-06-01 Startup takes a novel design-for-yield approach
Anchor Semiconductor says it offers the market's first silicon design-rule-checking tool.
2004-04-14 Startup takes a novel design-for-yield approach
Anchor Semiconductor has begun shipments of NanoScope, a tool that provides full-chip, post-resolution-enhancement technology verification.
2001-06-22 Solution space analysis for high-speed design
Up-front SI analysis can drive placement and routing while providing a viable alternative to the old "route-analyze-fix" approach of yesteryear.
2007-05-30 Routing suite receives 45nm design update
Gearing up to deal with 45nm IC physical design challenges such as interconnect resistance, Sierra Design Automation Inc. this week is announcing three significant enhancements to its Olympus-SoC placement and routing suite.
2006-06-19 Programmable chips rev critical algorithms
DRC and XtremeData deliver programmable coprocessors that can accelerate time-critical algorithms run on AMD64 processor.
2001-05-16 Practical IC design in the sub-wavelength regime
Demonstrated success of sub-wavelength lithographic processes has created the demand for a more robust, comprehensive design flow.
2015-05-28 Placing different voltage regions together
Whether you are concerned more about signal integrity or long-term reliability, the fundamental question is how close you can put different voltage regions before there are problems.
2010-08-26 Physical verification tool licensing program eases 65nm transition
Magma Design Automation Inc. releases introduces an initiative to facilitate designers' adoption of the design tolls for 65nm and below.
2005-03-16 PC-based tools lower barrier to MEMS
Take a closer look at how low-cost PC-based tools can help hurdle the challenges in MEMS design.
2013-06-06 Parasitic extraction in the double-patterning age
Determining the impact of double-patterning on electrical sign-off can be better achieved by understanding how PEX tools have evolved to handle this challenge.
2003-01-15 New RFIC design company launched
A team of engineers formerly with IBM Microelectronics' Wireless Division have formed a new radio and analog IC design company, Tahoe RF Semiconductor Inc.
2004-01-30 Motorola selects Mentor TestKompress, Calibre offerings
Motorola has selected Mentor Graphics' TestKompress embedded test tool for the manufacturing test, and the Calibre DRC and LVS physical verification tools.
2002-06-28 Motorola adopts Cadence's analog/mixed-signal design solution
Motorola Inc. has adopted Cadence Design Systems Inc.'s full-chip 3D device-level parasitic extraction solution called Assura RCX, for its analog and full-custom design flows.
2004-10-19 Micrel adopts DesignRuleBuilder to speed development
Micrel Inc. has adopted Stone Pillar Technologies Inc.'s DesignRuleBuilder component for semiconductor technology developments.
2002-06-03 Mentor Graphics Calibre to be integrated into TI's SoC designs
Texas Instruments is integrating Mentor Graphics Corp.'s Calibre physical verification tool suite to its ASIC, logic, mixed-signal and analog semiconductor processes.
2002-02-16 Mastering full-custom layout design
This technical article assists readers in defining the various flavors of full-custom layout design for them to choose the right type of tool for the right type of job.
2015-07-02 Making SoC power grids more robust
Read about a methodology that results in a robust power grid structure. Along with the robust design techniques, this methodology results in better silicon results.
2010-08-27 Magma Design Automation joins Si2's DFMC
The coalition also announces a 60-day review period for the first release of OpenDFM, a high-level DRC language that can be translated into a variety of proprietary verification languages.
2000-12-01 Integrated approach for emerging tech designs
This technology article describes the integration of clock tree synthesis with logic synthesis, placement route and interconnect extraction to maximize the potentials of cell-based designs.
2006-09-08 HyperTransport Consortium welcomes seven new members
The HyperTransport Technology Consortium, a non-profit organization dedicated to developing, promoting and licensing the HyperTransport interconnect technology, announced seven new companies as part of its commercial membership base.
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