Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > DfT

DfT What does TFT-LCD stand for? Search results

?
?
What does TFT-LCD stand for?
TFT-LCD stands for thin-film transistor - liquid crystal display. A TFT is a special kind of field effect transistor made by depositing thin films for the metallic contacts, semiconductor active layer and dielectric layer.
total search187 articles
2004-02-20 Teseda, Agilent certify STIL link between DFT, production test
Teseda Corp. and Agilent Technologies Inc. have announced the first link that ensures transportability of Design-for-Test (DFT) data between engineering and production test platforms, wherein customers of the Teseda V500 and the Agilent 93000 SOC Series can quickly and reliably validate, debug, and apply IEEE 1450 (STIL)-based production test data generated by EDA tools.
2002-10-03 Teseda ships DFT validation system for IC testing
Teseda Corp.'s DFT-focused validation system allows engineers to rapidly validate test for prototype ICs and cut time-to-volume production.
2003-04-03 TEL, Teseda rolls integrated DFT system
Tokyo Electron Ltd and Teseda Corp. have released an integrated design for testability (DFT) system targeted for wafer testing applications.
2006-03-31 Synopsys' DFT MAX reduces test costs on Nvidia GPUs
Synopsys announced that Nvidia has adopted Synopsys' DFT MAX Test Synthesis with Adaptive Scan technology for its next-generation graphics processor chips.
2005-03-11 Synopsys unveils next-gen DFT synthesis solution
Synopsys announced DFT Compiler MAX, its next-gen DFT synthesis solution, offering 1-pass test data volume compression capabilities to address design and test challenges occurring in 130nm and smaller process technologies.
2003-03-06 Synopsys DFT tool receives core add-on
Synopsys has integrated the SoCBIST add-on to its DFT Compiler for the creation of IP cores.
2004-05-25 STATS expands turnkey solutions with DFT capabilities
STATS has expanded its integrated turnkey solutions with DFT capabilities that will assist customers in improving testability and throughput of their devices.
2003-09-15 Silicon 'debug' product serves Synopsys DFT users
Claiming to dramatically speed test vector debug time for users of Synopsys' DFT products, Intellitech Corp. has announced the Nebula silicon debugger.
2010-11-03 Ricoh licenses DeFacTo's DFT solution
Ricoh Company Ltd announced the licensing of the HiDFT-Signoff Design-for-Test solution of DeFacTo Technologies SA.
2007-06-18 Rethinking DFT strategies in nanometer designs
As the industry races to the 90nm and 65nm nodes, manufacturers are exploring more advanced tests, a 'complete' solution with the most advanced test patterns and fault models needed to improve defect detection.
2002-04-01 Reducing fault-coverage analysis with DFT, Part 2
This technical paper is the second of a two-part discussion wherein the author considers fault-coverage analysis and simulation for full-scan testing of ASIC designs.
2002-03-16 Reducing fault-coverage analysis with DFT
This technical article is the first of two parts that considers how fault-coverage analysis and simulation for full scan testing of ASIC designs are equally applicable to other types of IC design, chiefly of which are FPGAs.
2001-06-01 Practical DFT leads to highly testable ASICs
Combine classic design-for-test methodologies, such as scan and BIST, with practical DFT, to clear the path to a highly testable design
2000-03-22 PADS-DFT Audit
This application note describes the PADS-DFT Audit. The Audit is an embedded design for test auditing tool that allows users to perform DFT analysis and verification before releasing the PCB for fabrication.
2008-05-13 NXP taps Mentor Graphics' DFT tools
Mentor Graphics's DFT products will be used by NXP Semiconductors to improve the quality and time-to-market of NXP's solutions.
2005-05-02 It's time to move DFT to a higher level
Today, the 'D' in DFT does not really stand for design. All too often, at the gate level, it stands for do-it-late.
2009-10-08 Improve yield with layout-aware DFT
This article discusses the approach to figure out those areas from the layout that has higher probability of physical malfunctioning. The design for test (DFT) tools can then generate top-up test patterns for these areas.
2013-01-24 Imec, Cadence team up for DFT solution for 3D memory
Cadence's and imec's solution includes generation of DRAM test control signals in the logic die and inclusion of the DRAM boundary scan registers test access mechanisms of the 3D test architecture.
2016-01-05 Enhance test quality, minimise DFT costs
Learn about two test solutions that can be implemented to exploit additional advantages of hybrid silicon test solution.
2005-08-16 DFT, DFM tests assure quality SoC design
Learn the importance of design-for-manufacturability and design-for-test in ramping up advanced products in deep-submicron technologies
2006-10-16 DFT rule checkers glue design together
Advances in DFT rule checking will likely continue as more designs depend on increasingly complex testing protocols.
2002-04-16 DFT confronts test cost in design run
This technical article offers a synopsis of the challenges in SoC design, particularly with regard to test costs.
2000-09-01 DFT and BIST for SoC designs
Design for testability (DFT) and built-in self-test (BIST) techniques are widely publicized in SoC (Systems-on-Chip) designs, but are still often only thought of as "back end" concerns. In reality, the importance of these techniques insures the highest fault coverage and shortest production test time in the device design cycle.
2011-04-06 ASTER rolls DfT, test coverage analysis tool
ASTER Technologies releases the first tool to provide an integrated workflow for DfT and test coverage analysis.
2015-12-29 What is lacking in Design for Testability?
The design part of design-for-test has been largely overlooked for far too long. In this article, we examine the hurdles and see what we can do to improve design activities for testability.
2003-09-24 Verification, test providers form outsourcing body
Six providers of services and tools for IC verification and test have banded together to form Expert Services and Tools for Semiconductors (ESTS).
2003-12-16 Using ISSP technology in structured ASIC design
NEC's ISSP technology for designing structured ASIC has become popular with design engineers because of its easy-to-use design flow and clear road map for 90nm.
2003-08-01 Unifying ESL, verification
Richard Goering says that the industry would need ESL and SystemC. But design for verification, with SystemVerilog, is the most obvious next step for most of today's RTL chip designers.
2004-06-10 TSMC selects Atrenta as Reference Flow 5.0 partner
Taiwan Semiconductor Mfg Co. (TSMC) has adopted Atrenta Inc.'s low power and ERC products as key enabling technologies in the company's latest Reference Flow 5.0. Both products from Atrenta include advanced solutions for clock domain analysis, DFT analysis, constraints analysis and automated functional analysis.
2004-05-03 Toshiba used Synopsys platform for SoC designs
Synopsys has announced that Toshiba has taped out multiple 90nm SoC designs for its audiovisual and office equipment product lines using Synopsys' platform.
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top