Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > Encounter digital IC design

Encounter digital IC design Search results

total search86 articles
2006-06-28 Routing solution speeds design to manufacturing
The Cadence Precision Router speeds design and manufacturing convergence for advanced mixed-signal, analog and custom digital designs
2003-06-24 Metalink adopts Cadence design platform
Metalink Ltd has adopted Cadence Design Systems' Encounter digital IC design platform.
2006-01-26 Fujitsu adopts Cadence Encounter GXL
Cadence announced that Fujitsu has adopted its Encounter digital IC design platform in its new internal reference design flow targeted at 65-nanometer chips.
2006-05-03 Fastrack Design standardizes on Cadence Fire & Ice QX Extraction
Cadence Design Systems Inc. announced that Fastrack Design Inc. is using Cadence Fire & Ice QX cell-based extraction technology to tape out a 65nm design for a consumer product
2005-03-03 Cadence, Virage team up to enable low-power design
Cadence Design Systems Inc. and Virage Logic Corp. have collaborated to provide library views to better address low-power, multi-voltage nanometer design needs
2006-09-08 Cadence, SMIC co-develop digital ref flow for 90nm tech
Cadence Design Systems and SMIC announced that they have jointly developed the low-power digital reference flow to support SMIC's advanced 90nm process technology
2004-10-11 Cadence, Artisan to optimize low-power chip design
Cadence Design Systems Inc. and Artisan Components have collaborated to provide library views that enable designers to effectively optimize low-power chip designs
2006-07-26 Cadence, ARM introduce first automated design for ARM Cortex-A8
Cadence Design Systems Inc. and ARM the joint development of the first automated RTL design and implementation flow for the ARM Cortex-A8 processor
2005-07-27 Cadence, Accent, ARM improve low-power design
Cadence Design Systems Inc. disclosed that Accent has validated a low-power design flow using its Encounter digital IC design platform and ARM Artisan physical IP.
2005-12-23 Cadence tech provides Intersymbol with reduced design cycles
Intersymbol has successfully qualified Cadence Design Systems' Encounter digital IC design platform in its mixed-signal design flow.
2005-02-08 Cadence teams with China IC maker for SCDMA transceiver
Cadence Design Systems Inc. said Friday (Feb. 4) a Chinese partner has begun sampling a dual-mode RF transceiver designed using Cadence design platforms
2004-06-04 Cadence supports Virage Logic ASIC design libraries
Cadence Design Systems Inc. is supporting Virage Logic Corp.'s area, speed and power (ASAP) Logic structured-ASIC metal programmable and standard cell libraries within the its Encounter digital IC design platform.
2003-08-15 Cadence platforms adopted by China-based IC design center
Cadence Design Systems Inc. has announced that China Suzhou CAS IC Design Center (SZ-CAS ICDC) has employed Cadence EDA platforms in its IC design platform
2005-09-15 Cadence offers shorter AMS design cycle
The AMS Methodology Kit from Cadence promises to enable analog mixed-signal designers of wireless, wired and consumer electronics devices to achieve shorter, more predictable design cycles while creating reusable AMS blocks
2004-11-18 Cadence Encounter Conformal 5.0 with enhanced verification capability
Cadence Design Systems announced enhancements to its Encounter Conformal technology
2004-12-17 Cadence Encounter assists NEC in supercomputer chip development
Cadence Design Systems Inc. has provided NEC Corp. with Encounter digital IC design platform to develop the complete 90nm chipset for its vector supercomputers.
2005-10-07 Cadence announces design flow for ARM Cortex-A8 processor
Cadence Design Systems announced the immediate availability of a high-performance design flow for the new ARM Cortex-A8 processor
2004-05-21 Aspex uses Cadence encounter platform
Aspex Semiconductor has taped out Linedancer processor from Cadence Design Systems Inc. using 130nm technology at 300MHz, and the Cadence Encounter digital IC design platform.
2006-08-30 Toshiba adopts Cadence solution for 65nm design
Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows
2005-06-10 Cadence's Encounter supporting Virage Logic's IPrima cell library
Cadence Design Systems Inc. and Virage Logic Corp. announced that Cadence's Encounter low-power digital IC design flow now supports power saving features of Virage's IPrima mobile semiconductor intellectual property (IP) platform's low-power standard cell library
2007-02-01 Cadence deploys CPF in low-power design flow
Cadence Design Systems has added the Common Power Format (CPF) to its existing logic design, verification and implementation tools
2003-09-02 Cadence brings 0.5?m design kit to China
Cadence Design Systems and IPCore Technologies jointly announced that they have cooperated to develop the first digital design kit for Central Semiconductor
2011-11-03 Perform assertion-based verification in mixed-signal design
Understand how assertion-based verification can address the challenges in analog/mixed-signal verification.
2010-05-21 Opinion: Custom IC design needs variation analysis
Incorporating optimal sampling and design-specific corner methods into variation-aware custom IC design can avoid costly over-margining or under-designing, and avoid delaying project schedules
2004-09-10 Cadence, UMC create sub-130nm IC reference flow
Cadence Design Systems Inc. and foundry United Microelectronics Corp. have announced an RTL-to GDSII reference flow for digital IC designs implemented in UMC's 130nm and lower processes
2003-09-17 Cadence rolls custom-IC tools into one platform
Cadence Design Systems Inc. has linked several acquired technologies with upgraded legacy tools to create an integrated custom IC design platform
2011-09-27 A primer on 3D-IC design challenges
Know the 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and learn how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals
2005-03-30 Concurrent' IC design suite rolls
Synopsys rolled out IC Compiler, which concurrently runs physical synthesis, clock tree synthesis, placement, routing, yield optimization and signoff correlation
2011-02-07 Solution speeds billion-plus gate design at 28nm
Cadence Design Systems Inc. has announced that it is advancing the design of giga-gate/gigahertz SoCs with digital end-to-end flow at 28nm
2004-06-11 Cadence adds DFM tools to Encounter
Cadence Design Systems Inc. said it has signed a multi-year business agreement with ASML MaskTools to co-develop design-for-manufacturing tools
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

Back to Top