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2005-05-11 Verific Design licenses HDL component software to Calypto
Calypto Design Systems Inc. has licensed Verific Design Automation's hardware description language (HDL) component software.
1999-10-01 Using parallel-distributed HDL simulation
Parallel-distributed simulations can reduce the time required to perform HDL simulations without dramatically affecting existing design flows. While the theoretical limit of parallel simulations is not reached, the simulation times do approach the limit within reason.
2003-11-25 Translogic HDL Companion targets complex designs
Translogic BV has announced that it has made its HDL Companion 1.0 available for free evaluation.
2003-05-15 Tool vendor @HDL licenses solvers from IBM
@HDL has licensed formal verification technology from IBM Corp. and plans to incorporate the technology into its current product line in the coming months.
2003-03-12 Spreadsheet tool generates HDL interfaces
The MatrixHDL tool allows users to enter interface descriptions and automatically generate VHDL or Verilog.
2003-12-10 Software yields graphical 'views' from HDL code
Novas Software Inc. will announce the Reusner Design Knowledge Publisher, which generates and automatically updates graphical "views" from HDL code. The views can be used for debugging or documentation.
2003-10-21 Researcher calls for new HDL approach for SoCs
A new approach to hardware design languages is needed in order to create a better "programmer's view" for SoC designs.
2005-06-06 Renesas selects Verific HDL component software
Renesas Technology Corp. has adopted Verific Design Automation's hardware description language (HDL) component software for use in its internal EDA environment
2002-09-20 Open-source tool offers HDL translation
An open-source tool created by the director of a small silicon IP company translates a subset of RTL VHDL into Verilog.
2003-01-14 Open-source tool converts HDL to HTML
An open-source tool from Millogic converts Verilog or VHDL code to HTML for Web browser viewing.
2002-05-27 ITC, HDL Dynamics enter IP core licensing agreement
Infinite Technology Corp. and HDL Dynamics have entered into an IP technology licensing relationship which includes ITC's OMNIcore RISC processor and RADcore DSP coprocessor IP.
2005-10-11 HDL tool suite cuts cycle times, respins
Mentor Graphics announced the release of a new concurrent design checking and creation environment, available in the latest version of the HDL Designer Series tool suite.
2004-03-30 HDL generation language adds open-source license
Confluence, a declarative programming language, is now available under the GNU General Public License.
2006-11-01 HDL Coder offers shortcut to IC design
The Mathworks Inc. offers the Simulink HDL Coder, which automatically generates synthesizable Verilog and VHDL from Simulink models and Stateflow diagrams.
2002-08-09 Engineer creates open-source HDL in Ruby language
Illustrating the power of the Ruby scripting language, consulting engineer Phil Tomson has used it to create the open-source Ruby hardware-description language.
2003-09-23 Engineer creates HDL generation language
A declarative, functional programming language that eases RTL code generation is now going into beta sites, and is available for free downloading.
2000-06-29 Chip-level HDL simulation using the Xilinx Alliance series
This application note describes the basic flow and some of the issues to be aware of for HDL simulation with Alliance Series software. It also familiarizes the user with some of the concepts but should not be considered a replacement for the Xilinx or HDL simulator's documentation
2000-02-22 An Introduction to Active-HDL Sim
The article provides a brief introduction of Active-HDL Sim post-fitting timing simulator and its role in the Warp design process.
2001-03-28 An introduction to active-HDL Sim
This application note provides a brief discussion to the Active-HDL Sim functional simulator. The discussion includes installing/uninstalling the simulator, creating an 1164/VHDL simulation model, the simulation process, and applying stimulus.
2001-03-22 An Introduction to active-HDL FSM
This application note provides an introduction to the Active-HDL FSM (finite state machine) editor, while highlighting key features of the software and illustrating the steps required to create a state machine.
2006-05-10 Aldec integrates Altera HDL support in simulator
Aldec announced that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment.
2005-01-04 Aldec blends SystemC, HDL debugging
Aldec released Riviera 2004.12. New features include integrated SystemC and HDL debugging, assertion-based verification, and functional code coverage.
2006-03-16 Accelerate design performance with HDL coding practices
Improve design performance by writing an HDL code that is efficient for your targeted device.
2001-03-20 Abel-HDL vs. IEEE-1076 VHDL
This application note compares and contrasts the complexity and basic features of Abel-HDL with those of IEEE-1076 VHDL.
2005-02-04 Xilinx extends support in Asia
Programmable logic solutions provider Xilinx Inc. has revealed expansion plans at its Shanghai office, in a bid to support customers in the Asia-Pacific region.
2003-03-21 Xilinx DSP tool reduces simulation times
The company has released the System Generator for DSP tool v3.1, which features hardware-in-the-loop and HDL co-simulation capabilities.
2005-12-16 Wrestling functional verification
Experts have differing views on how the design process can be improved so as to diminish the need for verification.
2015-11-23 What makes hardware emulation so compelling
Here is a quick assessment of the evolution of hardware emulators over the past two decades, comparing where things stood in the 90s to where they are today.
2006-03-16 Verifying mixed-signal designs
Each piece of a mixed-signal design presents difficult problems that can be solved only by producing a custom circuit that fits the requirements of its particular situation.
2005-09-01 Verification tech captures automotive expertise
The automotive industry calls for modern verification techniques as the proliferation of electronic gadgetry adds to rising IC complexity in cars
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