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2010-04-26 Understanding high-level synthesis design's advantages
It is vitally important to verify the design before performing high-level synthesis, not after. It is not effective to synthesize a design that does not work.
2003-12-23 Tool promises parallelizing synthesis
Touting a new approach to parallelizing, high-level synthesis, the Center for Embedded Computer Systems at the University of California at Irvine has released its Spark synthesis tool to engineers. Available as a free download, Spark takes C-language input and produces register-transfer-level VHDL code.
2006-05-29 ST certifies Mentor Catapult C Synthesis Libraries
Mentor Graphics announced that STMicroelectronics has added Catapult C Synthesis libraries to its standard ASIC design kit
2004-03-25 MIT technology fuels startup's synthesis tool
EDA startup Bluespec Inc. this week will announce an exclusive license from the Massachusetts Institute of Technology (MIT) for synthesis technology based on term rewriting systems (TRS
2005-05-27 Mentor Graphics synthesis tool evaluates Sanyo's LSI design
Mentor Graphics Corp. announced that Sanyo Electric Co. Ltd has selected the Mentor Graphics Catapult C Synthesis tool after an evaluation comparing high-level synthesis tools.
2005-03-10 Fraunhofer IIS selects Mentor Graphics Catapult C Synthesis tool
Mentor Graphics Corp. announced that the Fraunhofer Institute for Integrated Circuits IIS has selected the Mentor Graphics Catapult C Synthesis tool for use in next-generation digital broadcast applications
2003-12-09 EDA startup pioneers assertion-based synthesis
Startup Bluespec Inc. will preview an "assertion-based" synthesis technology next week that it describes as a new approach to chip design
2012-04-03 Developing NAND flash controller with high-level synthesis
Read about the application of a commercial HLS tool to a NAND flash controller with an error correction code block.
2014-12-04 Calypto intros high-level synthesis tech to speed up design
The Catapult 8 with the configurable hierarchical design architecture is built on a completely revised architecture that expedites design and verification closure, pushing widespread adoption of HLS.
2010-06-25 A high-level synthesis methodology for complex FPGA
This article describes the implementation of Virtual Line Crossing Detection (VLCD) on an Altera Stratix II FPGA and the methodology we used.
2006-01-13 Using software synthesis for multiprocessor OS and software development
The next great revolution in computer architecture is certain to be multiprocessing, just as it has always beenalways right around the corner.
2007-02-08 Reusable IP enhances ESL synthesis
Bluespec's AzureIP library brings reusable IP to an ESL synthesis tool that starts at a much higher level of abstraction and produces RTL code
2013-07-30 Reduce SoC power use without high-level EDA tools
Read about several situations where high level design tools are not useful and are sometimes a hindrance
2000-05-01 Long road ahead for analog synthesis
It may be a bit like asking why can't women be more like men, but the question, "Why can't analog be more like digital?" is the most common complaint among engineers attempting to use analog design tools. Synthesis (the automatic generation of physical circuitry from a high-level language description) is one area where analog design departs drastically from digital.
2004-05-12 Forte synthesis tool accelerates RTL delivery
Forte has disclosed that its Cynthesizer is the first behavioral synthesis product to offer an implementation path from SystemC to RTL, verification and co-simulation
2004-06-01 Embedded synthesis enhances high-density FPGA tools
Tools developed specifically for deep submicron programmable devices are emerging, enabling 100,000 gate and greater FPGAs to become mainstream choices.
2002-03-07 CoWare adds bus synthesis to N2C system
CoWare has enhanced its N2C design system with what it calls second-generation Interface Synthesis capabilities, which enable automatic synthesis of the bus interconnect matrixes and crossbar switches at the heart of multilayer buses in current SoC designs
2004-06-01 Behavioral synthesis crossroad
Ten years after its market entry as the next generation in synthesis, Synopsys' Behavioral Compiler is dead. Can somebody else breathe new life into behavioral synthesis
2007-04-16 AzureIP library accelerates ESL synthesis
Claiming to set a new direction for silicon intellectual-property (IP) design and reuse, Bluespec Inc. has rolled out the AzureIP Foundation Library, a set of parameterized IP blocks for use with the company's Bluespec Compiler.
2009-06-23 Asynchronous synthesis tool uses standard languages
Tiempo AS will demonstrate what it touts as the first synthesis tool for asynchronous logic that operates from standard design languages at the Design Automation Conference
2008-09-02 Achieve efficiencies with algorithmic synthesis
Algorithmic synthesis moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings
2001-05-01 Synthesis route starts with instructions
General-purpose instruction processors have dominated computing for a long time. However, the need to customize instruction processors for specific applications is now acute in embedded systems.
2004-05-19 Lighthouse introduces synthesis tools for Verilog test
Promising to reduce testbench development time by up to 80 percent, startup Lighthouse Design Automation Inc. will introduce tools that synthesize Verilog testbenches from high-level specifications
2011-02-02 Xilinx acquires EDA vendor AutoESL
Xilinx has acquired high-level synthesis vendor AutoESL in hopes of serving more companies whose system architects and hardware designers work at a higher level of abstraction in C, C++ and System C.
2011-09-01 Speeding up medical imaging process using FPGA
Read about the use of FPGA platform and a synthesis tool called Impulse C to speed up a statistical line of reaction estimation for a high-resolution PET scanner
2011-06-23 NEC targets U.S., European design houses with HLS tool
With CyberWorkBench, NEC hopes to serve U.S. and European design houses requiring high-level chip synthesis tools that address both data and control paths of their designs.
2005-06-13 Mentor Catapult C supports Panasonic network equipment apps
Mentor Graphics Corp. announced that Panasonic Communications Co. Ltd has selected the Mentor Graphics Catapult C Synthesis tool after evaluating other high-level synthesis tools.
2010-09-09 HLS tool allows designers to focus on ASIC differentiation
Mentor Graphics' Catapult C tool for the high-level synthesis (HLS ) of next-gen ASICs has been deployed by Toshiba.
2014-06-04 Designing for all programmable era: The essentials
Here's a check list of must-haves when considering some key features and best practices that design teams should look to incorporate in order to achieve faster time to market.
2007-10-18 Design flow improves DSP Fmax performance
Mentor Graphics and Altera have unveiled a design flow that delivers 50-80 percent DSP Fmax performance improvements, provides a low-effort path to dedicated DSP hardware creation and gives companies a cost-per-channel advantage over discrete DSPs.
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