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2013-11-08 Samsung, SK Hynix set to unveil next-gen memory chips
Samsung will demo low-power DDR4 SDRAMs for smartphones while SK Hynix will unveil its High-Bandwidth Memory, a stack of four memory chips fueling next-gen comms, graphics and server chips
2011-12-06 Production begins for 128GB/s hybrid memory cube
IBM's 3D chip-making process, the 32nm TSV technology, will create Micron's Hybrid Memory Cube.
2012-05-10 Microsoft joins memory consortium
Microsoft's participation signals the potential of the Memory Cube to drive changes in the traditional memory hierarchy and systems software for computers and networks
2014-02-05 Micron exec hints at novel memory chips, processors
In a keynote at DesignCon, Thomas Pawlowski said new kinds of memory interfaces and chips, and processors are coming that will offer more performance and new capabilities for engineers who adopt them
2014-08-26 Memory process roadmap soldiers on amid looming 3D tech
The constant reduction in feature sizes used to make ICs has improved memory-chip performance by increasing per-chip storage capacities, lowering power consumption, and improving data storage speed
2012-07-06 Hybrid Memory Cube group adds ARM, HP, SK Hynix
Hewlett-Packard and SK Hynix join Micron and Samsung in an effort to achieve an open interface for stacked memory
2013-04-04 Hybrid Memory Cube Consortium to focus on faster DRAM
Micron, Samsung, Hynix are among over 100 companies releasing a specification for a 3D DRAM and logic module known as the Hybrid Memory Cube.
2014-09-23 Future memory devices: 10 technologies to keep in mind
While current memory types are smarter and built with higher density, the succeeding memory technologies will integrate new types of materials, as well as smarter algorithms that make storage a hierarchy off-chip in a way that cache memory is hierarchical on-chip
2014-12-04 End of DDR marks surge of 3D, TSV-based memory
Several DRAM memory architectures based on 3D layer stacking and TSV have evolved to accommodate increasing memory requirements spearheaded by Samsung, Hynix and Micron
2014-07-10 Emulator runs pre-silicon verification of memory SoCs
The Veloce2 from Mentor Graphics is enables verification engineers to develop and stress test software and hardware on SoCs using HMC, LPDDR4, and eMMC 5.0.
2016-05-02 Data inspection techniques for massive memory designs
Learn about efficient data inspection techniques that will help you reduce the verification stint in a large storage high bandwidth DDR-based memory design
2011-10-12 Consortium to develop hybrid memory standard
Micron and Samsung aim to develop a memory standard that combines DRAM and logic processes in a single unit
2011-06-13 Alliance pushes for next-gen memory tech
Open-Silicon and Micron have announced their partnership that will enable them to create next-generation memory solutions focused on data networking and high-performance computing markets
2014-06-12 Semtech reveals HMC-compliant PHY IP
The Snowbush 28nm platform physical layer IP has met the interoperability requirements of the Hybrid Memory Cube standard with significant margin and passed the testing required by Micron.
2013-11-22 Pico Computing makes noise with blade server release
The EX-800 blade server features the combination of a hybrid memory cube (HMC) and four Altera Stratix V FPGAs (providing 3.6M FPGA gates).
2014-04-17 Niche SRAM market thrives in networking, telecoms
Given the memory's speed capabilities, SRAM finds success in networking, where infrastructures are regularly updated in order to manage moving and storing data, and keep up with the growing Internet traffic
2013-02-12 Micron to put flash, DRAM on DDR4 bus
Micron will include NAND flash and DRAM on the DDR4 bus to jump ahead of current solid state drives on PCI Express.
2012-08-16 Initial draft of 3-D DRAM specs released to HMCC members
The Hybrid Memory Cube Consortium has release a draft of interface specifications for its 3-D DRAM memory stack.
2012-12-14 IBM showcases 3D server chip stacks
IBM has showcased its techniques for stacking 45nm processors at IEDM. The company's techniques could give the processors significant performance and power gains.
2014-04-21 DRAM interfaces see favourable future
Wide-IO promises to provide a wider, faster bus for communication, while reducing interface power consumption to a fraction of today's level.
2014-03-13 Consortium releases HMC specification update
HMCC's update acknowledges existing industry nomenclature by migrating the associated channel model from SR to VSR, while the USR definition also increases performance from 10Gb/s up to 15Gb/s.
2016-01-06 AMD shares details about GPU using 14nm FinFET process
The Polaris chip, also known as AMD's GCN 4.0, was shown running at less than 86W compared to 152W for a current GPU, with both chips running the same videogame at 60fps and 1080-progressive resolution.
2013-09-06 Altera, Micron demonstrate FPGA and HMC interoperability
The demonstration provides an early proof point that production support of HMC will be delivered with Altera's Generation 10 portfolio and includes both Stratix 10 and Arria 10 FPGAs and SoCs.
2012-09-04 40G/100G Ethernet IP aimed at networking IC dev't
Open-Silicon and CoMira Solutions released the 40G/100G Ethernet media access controller IP and 40G/100G physical coding sublayer IP, touted as complete IP solution for networking applications.
2013-11-29 Shrinkage rate in NAND flash exceeds Moore's Law
Though a place remains for spinning-disc media and DRAM, NAND flash memory is assuming an increasingly important role, not just in storage, but also in embedded systems
2012-03-28 Micron advances with 3D chips
The company has laid down its plans with the Hybrid Memory Cube that is currently being backed by Altera, OpenSilicon, Samsung, Xilinx and IBM.
2012-08-27 Interconnects enter Intel, ARM server battle
Recent developments in interconnect technology could prove useful for various chip-to-chip uses such as high-speed networking and future stable memory interfaces
2015-03-26 Intel bares Xeon Phi with 72 cores
The Xeon Phi Knights Landing will house more than 60 cores (rumoured up to 72) intimately married to a special version of Micron's Hybrid Memory Cubes mounted in-package
2014-11-27 How to achieve 200-400GE network buffer speeds
Know how a serial chip-to-chip protocol, with 200-400 GE data rates and 4.5 B read/write transactions, can be used to eliminate throughput bottlenecks at the processor/external DDR memory interface
2014-05-05 Exploring Samsung 2x nm LPDDR3 DRAM
Know some of the challenges faced by memory makers as they strive for sub-20 nm devices
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