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IC design verification What does IC design verification mean? Search results

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What does IC design verification mean?
IC design verification refers to the process of determining whether or not the design of a product, of a given development phase, satisfies the conditions imposed from the start.
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2009-03-02 Verification tools receive upgrades
Jasper Design Automation's ActiveDesign with behavioral indexing is an IC design tool billed as enabling design engineers to capture and preserve intended design behavior as it is being implemented
2002-08-30 Synopsys to acquire IC design verification firm
Synopsys Inc. has signed a definitive agreement to acquire all outstanding shares of Co-Design Automation
2002-06-18 Quickturn upgrades design verification system
Quickturn has upgraded its Palladium design verification system to provide higher simulation-acceleration performance and support configurations of 2-million to 128-million ASIC gates, as well as up to 64GB of memory and >8,000 physical I/Os for target system interfacing
2015-10-05 MEMS design, manufacturing on the microscale
The microelectromechnical system is a source of wonder in this modern world, so too is its design and manufacturing. Find out why
2011-07-28 IC design platform promises increased productivity
Mentor Graphics' Pyxis Custom IC Design Platform features advances in concurrent design and automated custom IC routing technology
2010-05-18 Wipro taps Mentor tools to reduce design time
Mentor Graphics Corp. and Wipro Technologies are partnering to continue to enable time-to-market and first-time right solutions to their global product engineering customers.
2002-10-01 Verplex: Solutions for correct RTL design implementation
Taiwan started promoting electronics in the 1980s as part of its key economic development initiatives.
2002-03-11 Verification tool enables rapid ASIC prototyping
Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification environment addresses all hardware prototype creation and verification challenges
2013-02-12 UMC, Synopsys partner for design verification at 28nm
UMC selected Synopsys' IC Validator physical verification product for lithography hot-spot checking to accelerate physical signoff at 28nm
2002-09-16 Ultrasparc III passes physical verification
Sun Microsystem's new processor succeeds in its quest to make optimal use of the die area and power budget to achieve highest performance.
2008-06-05 TSMC stirs IC designs using 40nm node
Paving the way for next-generation chips, TSMC is set to roll out its latest design methodology for IC production at the 40nm node
2012-09-21 The golden age of simulation-driven design
Find out what it takes to design for reliability nowadays
2004-01-14 Tanner adds design tool
Providing a low-cost alternative for IC DRC, Tanner EDA has introduced HiPer Verify, the first product in the company's new HiPer line of layout and verification products
2007-09-20 Taiwan's MediaTek adopts Mentor's formal verification tech
Mentor Graphics announced that Taiwan's MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects
2007-02-21 SystemVerilog falls short for design
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support
2004-02-24 System-level design seeks traction
The move to system-level design, which is seen as critical as the industry moves to 90nm and lower, has been slowed by a lack of investment, doubts about any quick return on investment along with a shortage of systems designers and standards, U.S. experts said
2007-05-16 Survey: Taiwan IC design aims for high-end CE
The "2007 Taiwan IC Design House Survey" revealed a maturing chip design industry that's ready to take on more complex challenges to carve a name for itself in this highly competitive business
2003-08-19 Startup turns to China for analog design suite
Paragon IC Solutions is a two-year-old EDA startup that's selling an analog IC design suite with a 13-year heritage
2004-04-14 Startup takes a novel design-for-yield approach
Anchor Semiconductor has begun shipments of NanoScope, a tool that provides full-chip, post-resolution-enhancement technology verification
2004-09-16 Start thinking out of known 'design box
Package is not simple anymore: IC and package have become a whole and must be treated as such
2011-05-13 Software expands verification interoperability
Springsoft's Verdi debug software expands verification interoperability with complete UVM support enabling UVM code and better transaction-level analysis to ease debug of SystemVerilog testbenches
2002-11-18 SoC/IP designs need next-gen solutions for integration verification
As the cost of SoC design plus time-to-wolume pressure continue to rise, a next-generation simulator for SoC integration verification is required to ensure functionality
2006-11-06 Skill shortage, labor costs challenge India design
An inadequate number of skilled engineers due to lack of specialized institutes and advanced technical courses poses a big barrier to the growth of India's VLSI design business for the next two years
2002-05-23 Rival RF design flows get a boost
Two former software partners will square off at the Design Automation Conference next month with their respective RF IC design and simulation tools
2008-02-26 Rhines on EDA: End 'endless verification
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification
2005-08-01 RF IC tools still seeking paths to silicon
Complicated by multiple modulation schemes, RF tools have become proficient at simulating behavior on an architectural level.
2005-10-26 Researchers propose approach to cut design validation time
Five Indian researchers from the have proposed a new approach to formal property verification
2006-08-18 Realtek, Cadence collaborate on formal verification design
Cadence Design and Realtek Semiconductor announced that they have collaborated to successfully reduce the risk of functional errors on its pilot multi-supply voltage design
2003-03-19 R&D center in China to utilize Synopsys IC design tools
Synopsys Inc. has agreed to donate IC design tools to the High Technology Research and Development Center of the Chinese Ministry of Science and Technology
2007-05-17 Platforms upgrade custom IC, PCB design
Cadence Design Systems claims to have a "complete" custom IC simulation and verification solution, along with an advanced constraint-driven PCB design flow with announcing the release 6.2 of its Virtuoso MMSIM tool.
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