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2015-09-28 SiP, PVS tech enabled for TSMC InFO packaging
Cadence said the Allegro SiP design tools and PVS allow TSMC customers to cut the InFO design and verification cycle by offering an integrated solution that automates the design-rule checking (DRC) flow.
2011-04-28 Packaging tool offers advanced miniaturization
Cadence has unveiled the Allegro 16.5 PCB and IC packaging technology, offering capabilities that increase both productivity and predictability across silicon, SoC and system development.
2009-08-25 Vietnam IC manufacturing hits roadblocks
Vietnam has hit a few speed bumps along the road in its dreams to develop an IC manufacturing industry
2004-04-21 Vate Technology to beef up its mini-BGA output
Vate Technology Corp., a testing and packaging house, is set to expand its monthly capacity for mini BGAs
2008-04-30 TSMC IC design collaboration strategy stirs controversy
TSMC has unveiled a new and possibly controversial strategy that involves more collaboration in the early stages of the IC design process
2014-04-25 TSMC fleshes out IC line-up with shrunk TSVs
Based on its work on chip stacks, TSMC will launch in July an enhanced version of the 16nm FinFET technology with up to 18 per cent faster data rates and lower leakage, in addition to a planned 10mm and 7mm processes
2011-04-11 TSMC enters chip-packaging arena
TSMC will soon open a bumping facility and offer silicon interposers and TSV technologies for 3D chips, but will remain focused on the foundry market and will not compete against subcontractors.
2012-10-11 SPTS signs JDP with Fraunhofer for 300mm 3D IC Apps
The program will use 300mm APM plasma enhanced chemical vapor deposition modules installed on a Versalis platform alongside SPTS etch chambers in the ASSID centre in Germany.
2011-09-26 Specialized foundry processing yields high-performance analog IC
Learn about the impact of foundry process on achievable specifications.
2011-12-20 Rambus, ITRI team up for 3D packaging
According to the two organizations, they will work together as members of Ad-STAC to push system integration using silicon interposer technology
2006-11-13 Outsourced IC packaging to reach $13.1B
The market scale of outsourced IC packaging is estimated to hit $13.1 billion in 2006, with Taiwan gradually becoming a powerhouse in the test and packaging industry segment, according to Research and Markets
2003-06-16 OSE, Winstek collaborate for high-end IC testing
Orient Semiconductor Electronics, an IC packaging and testing firm, has partnered with IC testing firm Winstek, to increase its testing capabilities
2011-05-10 Microchip acquires Thai IC-assembly firm
Microchip has decided to buy Millennium Microtech Thailand, a provider of assembly and test services for semiconductor manufacturers, instead of building its own IC-assembly plant
2009-10-19 ITRI, Applied Materials push 3D IC dev't
Applied and ITRI will work together as members of the Stacked-System and Application Consortium
2007-05-30 Inverter IC trims power use in white goods
Mitsubishi Electric Europe's M81500FP inverter IC is not only the world's smallest IPM for the 90W range but is also the first in its class is integrated in an SMD package
2007-11-14 Infineon reveals new packaging technology
Infineon Technologies unveils a new package technology, and has tapped Advanced Semiconductor Engineering as its IC packaging partner.
2003-01-16 IC suppliers ramp system-level design
Many IC suppliers are morphing into subsystem-level suppliers for system integrators, so chip companies must therefore master integration at multiple levels - from IC to board to system
2005-12-27 IC packaging providers upbeat
Continued strength in the IC packaging and test sector during the fourth quarter and possibly beyond has prompted an investment banking firm to raise its estimates for Amkor, Siliconware and STATS ChipPAC
2009-10-23 IC packaging becomes more challenging
Analog design remains challenging but IC packaging is becoming an issue in the arena
2005-07-08 IC packaging and testing companies expect high revenues in Q3
Most IC packaging and testing companies in Taiwan are anticipating significantly higher revenues in the second half of the year, as increasing demand has shown signs of market potential in June
2007-11-08 IBM-led alliance ups investment in 32nm packaging
The Common Platform alliance led by IBM plans to increase its investment in semiconductor packaging technology to pave the way to 32nm devices
2004-05-21 IBM jettisons IC-packaging units, sells plants to Amkor
IBM Corp. has moved to jettison its chip assembly and packaging operations, announcing a major deal with Amkor Technology Inc
2004-04-14 HKSTP, ASAT to promote chip packaging in HK, China
The Hong Kong Science and Technology Parks Corp. (HKSTP) has formed a strategic alliance with ASAT Holdings Ltd, a provider of semiconductor package design, assembly, and test services, to cooperatively promote IC packaging and test related services in Hong Kong and mainland China.
2006-07-17 Green IC packaging addresses environmental concerns
As new environmental regulations are enacted and a universal recognition of the benefits of Green design and manufacturing practices percolates, adherence to manufacturing regulations will become a basic requirement for participation in world markets.
2013-04-04 Globalfoundries delays 3D IC stack production
The company says it expects to use the 20nm process for 3D chips that may not ship in volume until 2015 or later.
2006-08-03 Freescale cuts die area, thickness with new chip packaging tech
Freescale's proprietary redistributed chip packaging technique delivers about a 30 percent reduction in packaged-die area and thickness
2009-02-12 Five ways to beat IC scaling roadblocks
Intel senior fellow and director of process architecture Mark Bohr listed five major stumbling blocksor challengesfor the 32nm node and beyond.
2010-01-06 Fearless IC forecasts for 2010
2010 is just beginning to unfold in the electronics industry and there is already uncertainty in the air. EE Times' Mark LaPedus offers his chip forecasts and other prediction for 2010.
2015-07-03 Examining 3D embedded substrate power packaging
Here is a look at 3D embedded substrate power packaging technologies, which will be increasingly deployed in everything from cell phones to hybrid electric vehicles
2003-04-28 Epson licenses Tessera packaging technology
Seiko Epson Corp. has entered a technology license agreement with Tessera Inc. to utilize the latter's semiconductor packaging technology in ASICs and specialty memory products
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