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2002-05-01 VSIA releases SI spec for IP-block integration
VSIA has released the initial version of a signal integrity extension to the specs to help intellectual-property suppliers communicate signal integrity data to IP integrators
2007-02-16 Integrate 'hard' IP into an SoC
During the course of delivering such IP over the past several years, Impinj has witnessed a range of IP integration experiencesfrom the painless to the nearly disastrous. Most of the pitfalls can be avoided by following a few recommendations
2006-10-10 VSIA forms verification IP quality workgroup
VSIA has formed a quality workgroup to create a verification IP quality worksheet that will address the challenges facing designers as they evaluate and implement standard verification IP components
2013-06-25 Utilising non-volatile memory IP in SoC designs
Integrating anti-fuse NVM on chip for program storage results to increased margin as well as independence from vagaries of supply chain and component availability.
2006-02-16 Quality metric upgrade may ease IP selection
Selecting silicon IP may get a little easier, as the VSI Alliance has released its QIP Metric 2.0 for free
2013-01-24 Discover the truth about analogue IP at 28nm
Know the truth about the three myths surrounding the economics of analogue block implementation in advanced process technologies
2012-06-11 DAC tackles the rise of IP subsystems
Executives on a Design Automation Conference panel believe that intellectual property (IP) reuse in SoC design is increasing, thus creating challenges in compatibility and complexity
2002-11-18 SoC/IP designs need next-gen solutions for integration verification
As the cost of SoC design plus time-to-wolume pressure continue to rise, a next-generation simulator for SoC integration verification is required to ensure functionality
2005-01-17 RTOS operations put in hardware IP
Ingios has created a block of hardware IP that handles task scheduling and intertask communications
2005-01-03 Reality check for configurable IP blocks
Configuring IP subsystems in Bluetooth within existing architectures can now be overcome through a more holistic approach
2010-02-01 PHY IP solution eases HDMI 1.4 integration
Synopsys Inc. has launched the high-quality DesignWare HDMI 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification
2006-08-16 Mobile-TV tuner, GPS block due from Chipidea
Chipidea recently announced new IP blocks for mobile TV and global-positioning systems. The company also has ultrawideband and wireless sensor products in design
2013-06-07 Maxim CEO talks analogue, strategic integration
Maxim Integrated's Tunc Doluca discusses his new 90nm analogue process, his integration strategy, Intel, Samsung and China
2008-06-24 Low power design for analog/mixed-signal IP
Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase.
2008-09-30 Intel, Chartered criticize chip IP industry
The semiconductor intellectual property (IP) industry has been the virtual and ongoing punching bag in the IC business
2008-07-22 DesignWare SATA IP solution rolls for disk drives
Synopsys Inc. announced the availability of the DesignWare SATA Device IP, for use in applications such as solid-state drives, HDDs and optical disk drives
2012-01-11 Address hardware/software integration issues with combined prototyping solutions
Find out how to reap the individual advantages of prototypes in combination with other prototyping techniques.
2001-06-01 Extraction method verifies IP functions
To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process.
2006-08-10 Chipset suit IP telephony, modem, line monitoring apps
The new chipset from Integration Associates is voice and V.92 capable and is suitable for telephone line interface requirements and standards
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams
2004-12-16 Mentor SoC design tool supports SPIRIT 1.0
Mentor Graphics announced that its Platform Express product now supports the SPIRIT 1.0 specification for intellectual property design re-use.
2004-04-28 Giga Scale tweaks IC prototyping
Giga Scale IC will announce its InCyte product family, which lets users estimate and optimize design objectives such as timing, area, power, leakage and yield.
2012-12-24 Easing system simulation with hardware models
Hardware models can accelerate integration and system verification tasksif they are available early enough in the design flow
2006-10-06 Coalition seeks to unify IC power standards efforts
The Silicon Integration Initiative launched the Low Power Coalition which may help unite two disparate efforts for standardizing a power specification format
2014-01-15 Cadence unveils Incisive 13.2 for SoC verification
The Incisive 13.2 platform from Cadence Design Systems offers features two new engines and additional automation features to speed SoC verification closure.
2005-12-20 ZiLOG MCU in ARRIS E-MTA with VoIP
ZiLOG announced that ARRIS has selected its Z8 Encore! XP MCU for use in the design of its next-generation Embedded Multimedia Terminal Adaptor (E-MTA) with VoIP, the Touchstone Telephony Modem TM502.
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2004-03-16 Synthesis methods for ASIC, FPGA designs
Design methodologies that employ cross-implementation EDA technology such as the MultiPoint provide the flexibility to implement a design in the best possible medium.
2008-03-07 Synopsys enters embedded memory market
Synopsys Inc. has announced the expansion of its DesignWare IP portfolio with the addition of an SRAM-1T embedded memory IP that is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs
2014-01-05 SoC implementation with dependable 50% duty cycles
Here's a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power.
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