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2001-06-01 ASIC generation revamped for IP reuse
For designers, the linchpin for complete IP reusability is the programmable VLIW processor core, along with programmable buses and interface ports
2003-12-18 Aptix releases prototyping system for block and IP designers
Aptix Corp. has developed a relatively small, inexpensive FPGA-based hardware-prototyping system for intellectual-property and IC-block design
2008-11-17 Antifuse memory IP offers lower-power operation
Memory IP for power-sensitive apps requires the design of both the basic memory bit and the memory macro architecture to minimize power demands
2005-09-01 Actel's new IP core generator promises optimized FFT cores
Actel introduced CoreFFT, an intellectual property core generator that promises optimized fast Fourier transform (FFT) cores for use with the company's flash- and antifuse-based families of FPGAs.
2001-06-01 Extraction method verifies IP functions
To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process.
2006-08-10 Chipset suit IP telephony, modem, line monitoring apps
The new chipset from Integration Associates is voice and V.92 capable and is suitable for telephone line interface requirements and standards.
2002-01-22 Amphion launches WLAN baseband IP cores for 802.11a and HiperLAN2
Providing solutions for PHY implementations of IEEE 802.11a and HiperLAN2, the CS3720 transmit and CS3820 receive cores use direct-mapped DSP functionality to accomplish end-to-end WLAN baseband processing.
2003-08-01 Unifying ESL, verification
Richard Goering says that the industry would need ESL and SystemC. But design for verification, with SystemVerilog, is the most obvious next step for most of today's RTL chip designers.
2006-06-26 Reusable virtual components gain popularity with SoC
The crash of 2001 spelled disasters for pure IP companies who had not yet established brand loyalty. Many were bought out by more established companies, while others simply shut down for lack of revenues
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams
2006-01-16 NoC: A new venue for system innovation
The SoC concept has evolved through a number of design challenges over the years and so has the number of semiconductor IP blocks
2004-12-01 Methodology sought for assertion-based verification
Silicon IP providers and creators seek guidelines on how to use assertions effectively, aside from the standard protocols
2004-12-16 Mentor SoC design tool supports SPIRIT 1.0
Mentor Graphics announced that its Platform Express product now supports the SPIRIT 1.0 specification for intellectual property design re-use.
2003-06-02 Hybrid FPGA/ASIC devices address market needs
Hybrid FPGA/ASIC devices allow instant design changes like FPGAs, while leveraging the more efficient ASIC logic for fixed blocks of a design.
2012-12-24 Easing system simulation with hardware models
Hardware models can accelerate integration and system verification tasksif they are available early enough in the design flow.
2013-09-26 Design Linux-based femtocell base-station (Part 2)
Here's the second of a two-part series on building a wireless femtocell with a base station SoC powered by a Linux-based fast-path software architecture.
2006-01-02 Denali's Blueprint supporting Spirit 1.1
The company's Blueprint ESL tool now supports version 1.1 of the Spirit Consortium's specification for packaging IP
2004-09-15 Cost pressures spotlight design reuse
The ultimate ultra-low-k material that complies with future microelectronics has not yet been found.
2014-01-15 Cadence unveils Incisive 13.2 for SoC verification
The Incisive 13.2 platform from Cadence Design Systems offers features two new engines and additional automation features to speed SoC verification closure.
2001-08-09 Application driven optimization of the next-generation Bluetooth solutions
This conference technical paper presents an overview of the first-generation Bluetooth solutions that target many applications with a generic product offering.
2012-03-30 Altera rolls its 28nm Cyclone V FPGAs
According to the company, the products are the lowest power and lowest cost 28nm FPGAs on the market geared for the industrial, wireless, wireline, military and automotive markets.
2013-11-21 Advantest offers cloud as electronics testing sol'n
Targeting IC design departments, academics and R&D, Advantest's platform taps the productivity potential of the cloud without compromising testing data confidentiality and availability.
2006-03-13 Actel infrastructure enables mixed-signal systems deployment
Actel unveiled an expanded design infrastructure in support of its single-chip M7AFS device, the ARM7-enabled version of the company's Fusion programmable system chip.
2004-05-03 'Algorithm-to-tapeout' synthesis rolls
Synfora has unveiled a tool that lets users design compute-intensive blocks from C-language algorithms.
2005-12-20 ZiLOG MCU in ARRIS E-MTA with VoIP
ZiLOG announced that ARRIS has selected its Z8 Encore! XP MCU for use in the design of its next-generation Embedded Multimedia Terminal Adaptor (E-MTA) with VoIP, the Touchstone Telephony Modem TM502.
2004-05-04 Xilinx rolls out CPCS reference design
The company has launched a free fully functional CPCS reference design for a multi-mode PCS block implemented in Xilinx Virtex-II Pro FPGAs
2002-03-06 VSIA takes hard look at embedded software reuse
The Virtual Socket Interface Alliance has set up a development working group to create standards for the reuse of embedded software, in a bid to address what may be the next big challenge in SoC design.
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective.
2015-05-11 Verilog-AMS vs SPICE view for DDR, LCD verification
In this instalment, we comparatively analyse the usage of both views from the perspective of DDR interfaces, LCD controllers and on-chip memories.
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