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1999-10-01 Using parallel-distributed HDL simulation
Parallel-distributed simulations can reduce the time required to perform HDL simulations without dramatically affecting existing design flows. While the theoretical limit of parallel simulations is not reached, the simulation times do approach the limit within reason.
2004-03-16 Synthesis methods for ASIC, FPGA designs
Design methodologies that employ cross-implementation EDA technology such as the MultiPoint provide the flexibility to implement a design in the best possible medium.
2008-03-07 Synopsys enters embedded memory market
Synopsys Inc. has announced the expansion of its DesignWare IP portfolio with the addition of an SRAM-1T embedded memory IP that is implemented in bulk logic CMOS technology, requiring no additional manufacturing costs
2005-04-29 Synopsys DesignWare supports GUC SoC designs
Synopsys Inc.'s DesignWare intellectual property (IP) has been chosen by design foundry Global UniChip (GUC) for use in complex system-on-chip (SoC) designs
2014-01-05 SoC implementation with dependable 50% duty cycles
Here's a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power.
2003-06-02 Security risks threaten FPGA designers
The rapidly growing importance of FPGAs and microprocessors in systems, plus increasing time-to-market pressures, has led to security being 'overlooked' in most systems.
2005-08-10 Revised model-based DSP tools pitch higher performance
The 2005.3 versions of AccelChip DSP synthesis tool and related intellectual property core generators for MATLAB model-based design of DSP products promise higher performance circuits and higher speed
2005-08-30 Revised model-based DSP tools pitch higher performance
The 2005.3 versions of AccelChip DSP synthesis tool and related IP core generators for MATLAB model-based design of DSP products promise higher performance circuits, higher speed, and streaming I/O microarchitectures for FFTs
2015-09-16 Resolving giga-scale challenges in memory design
Advanced designs are more complex and larger than ever before, and designers are balancing between accuracy and performance for large scale memory simulation and verification.
2014-12-04 Protecting FPGA system with secure authenticator
Learn about the general problems that counterfeiters pose for original equipment manufacturers and end customers, and how these concerns can be addressed.
2009-08-14 Porting uIP1.0 to LPC1700
This application note describes the steps and details of porting uIP (a light-weight TCP/IP Stack) to LPC1700. A simple Web server is implemented as a demo
2002-11-18 Plugging the verification time sink
Logic equivalence checking provides an independent means of verifying the design process and reduces the overall verification effort.
2003-08-06 PalmChip bus patent threatens most SoCs
A patent granted to PalmChip covers the techniques used to implement on-chip CPU bus structures in nearly all modern system-on-chip designs.
2006-08-24 On Demand readies multimedia IC for 2007 launch
On Demand Microelectronics AG is embarking on an aggressive IP strategy to bring new programmable solutions for multimedia applications currently done in hardware
2003-06-16 Networked multimedia success hinges on DSP selection
Selecting DSPs for networked multimedia is complex. One must understand the attributes that could make the difference between a marginal implementation and a robust solution.
2006-08-16 Mindspeed rolls video processor IC, DSP cluster
Mindspeed Technologies Inc. simultaneously launched a seventh generation of its Comcerto VoIP processor and a software suite that includes protocols for 3GPP and IP Multimedia Subsystems
2015-01-22 Memory VIP speeds up mobile design verification closure
The added features of Synopsys' verification IP portfolio will enable project teams using the JEDEC UFS, MIPI UniPro and JEDEC eMMC protocols to expedite verification closure of mobile and SoC designs
2007-06-26 MCUs offer high performance at lower power, cost
Atmel Corp.'s customizable MCU delivers up to 8x the performance for DSP algorithms frequently implemented in FPGAs, with reduced power consumption and unit IC costs that are 30-50 percent lower.
2004-10-18 LSI Logic takes aim at PCI Express
Targeted to the needs of PCI Express developers, LSI Logic announces a new family in its RapidChip structured-ASIC line.
2006-09-18 Leverage ESL with legacy RTL
Platform-based design lets designers automatically integrate ESL modules with existing RTL IP. John Wilson gives his tips and tricks
2003-07-16 iSCSI silicon taken to new price point
Higher chip integration often creates a new price point that can spur growth in a burgeoning market. And iReady Corp. hopes to do just that with an iSCSI storage-networking device it has developed with National Semiconductor Corp.
2008-04-01 IPTV calls for content-aware network edge devices
IPTV is very different from traditional cable/satellite TV services and will place significant new demands on telecom network infrastructure. Here's a look at how IPTV presents new packet processing demands at the edge.
2003-04-16 Internet Protocol lands a role in SANs
With today's high demand for flexible, storage architectures such as SANs and NASs, IP-based storage is the best bet when interoperability and total cost of ownership is considered
2005-01-17 Inside a hybrid verification model
The combination of languages, tools, IP and methodologies has morphed the traditional ASIC design cycle into a 'hybrid model' process. Learn more
2004-09-01 Infiniband delivers flexibility
Infiniband as a backplane technology offers new flexibility that allow for rapid remapping of applications.
2006-12-15 India's L&T Infotech acquires US electronics design firm
As part of its plan to offer end-to-end solution delivery capabilities, Larsen & Toubro Infotech Ltd has acquired electronic design firm GDA Technologies Inc.
2006-08-16 Implement broadcast video infrastructure
PLDs will play an increasingly important role in the digital buildup of the broadcast industry infrastructure.
2014-10-16 How to improve FPGA comms interface clock jitters
Know how external phase locked loops can be used to resolve problems faced when dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes.
2012-09-04 Growing audio needs in SoCs
There is a growing list of audio requirements such as a wider range of high-definition audio compression formats, multichannel audio content, higher sampling rates and advanced audio post-processing functions.
2013-06-17 Global ECB disc storage market hit $5.5B in Q1
Gartner said the worldwide external controller-based disc storage vendor revenue registered a 0.6 per cent increase from revenue of $5.4 billion in 1Q12.
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