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2013-07-09 USHIO books its interposer stepper for 2.5D/3D packaging
The UX7-3Di LIS 350 has achieved a resolution of 2?m L/S on a 300mm Si wafer as well as an organic substrate and is able to address a warp or expansion/contraction of an organic substrate.
2011-12-07 IME, Tezzaron develop "2.5D" interposer tech
A*STAR Institute of Microelectronics and Tezzaron Semiconductor aim to refine the design and manufacture of silicon interposers and standardize the process, flows, and process design kits.
2012-12-20 A*STAR offers 2.5D through-silicon-interposer MPW service
The service is aimed at providing a cost-effective platform to do research and development prototyping and proof-of-concept in 2.5D TSI technology.
2009-11-13 Slot interposers validate DDR3 memory bus
Agilent Technologies and Nexus Technology have teamed up to support DDR3 DIMM or SODIMM validation, failure analysis and bus functional-parametric validation.
2011-12-20 Rambus, ITRI team up for 3D packaging
According to the two organizations, they will work together as members of Ad-STAC to push system integration using silicon interposer technology.
2011-02-04 Protocol analyzer eases DDR3 memory system design
Le Croy Corp. demonstrated four products at DesignCon2011: a protocol analyzer targeting DDR3, another protocol analyzer featuring small size and low ocst, an interposer card and a mezzanine card.
2001-04-01 Power distribution for high-performance processors
A new architecture not only addresses issues such as rising current transients, but also considers the limited space available for semiconductor devices and their associated power delivery systems.
2002-04-12 Nitto Denko yields ultra-thin printed circuit substrate
Electronics materials maker Nitto Denko Corp. has developed an ultra-thin, multilayer FPC substrate that features half the thickness of existing circuit boards.
2015-02-20 Keysight sol'n tests DDR4 x16 designs with logic analyser
The W4631A BGA interposer provides fast, accurate capture of address, command and data signals for debugging designs and making validation measurements.
2013-04-04 Globalfoundries delays 3D IC stack production
The company says it expects to use the 20nm process for 3D chips that may not ship in volume until 2015 or later.
2014-02-13 EVG outs high-volume-mfg photoresist processing system
The EVG150XT is optimized for ultra-high throughput and productivity and is aimed at logic and memory high-volume manufacturing.
2008-02-04 Contact interface promises high density, speed
Molex and Neoconix have partnered to deliver a flexible, copper-based high-density and speed interposer.
2012-11-16 Altera, Huawei incorporate FPGA, memory in 2.5-D tech
The new device will significantly reduce board space while increasing performance.
2013-06-25 A*STAR IME, IC firms team up to tackle industry issues
A*STAR Institute of Microelectronics launched the 2.5D Through-Silicon Interposer Consortium to speed market adoption of TSI tech, which is driven by demands in computer infrastructure and CEs.
2013-07-26 Metrology system configured for advanced packaging
Rudolph Technologies' metrology suite includes specially-designed configurations for wafer level packaging, 2.5D (interposer) and 3D ICs using through-silicon via (TSV) as interconnects.
2013-04-02 IME, UTAC team up for 2.5D TSI packaging solutions
United Test and Assembly Center will collaborate with A*STAR's IME to develop a 2.5D Through-Silicon-Interposer (TSI) platform for packaging solutions.
2002-07-11 High-frequency test socket rolls
Aries Electronics has broadened its line of high-frequency test sockets with a unit that has a replaceable spring probe interposer.
2004-01-26 Agilent analysis probe allows design, debug operations
Agilent Technologies has introduced what it claims as the industry's first interposer analysis probe for next-gen double data rate 2 SDRAM buses.
2015-07-28 A closer look inside SK Hynix's 1st high bandwidth memory
SK Hynix's HBM has a 1,024-wide bus. It employs a base logic die as an interface between the four DRAM die stack and an interposer that supports both the HBM modules and the AMD GPU.
2014-11-14 Worst practices for DDR memory testing
There are some things to watch out for when testing DDR memory deviceswe call them worst practices. These can adversely influence measurement accuracy or even wreck your probing setup.
2015-10-16 Wideband digital receiver touts higher processing capability
Keysight released what it says is an enhanced signal processing configuration for its M9703B 12bit AXIe high-speed digitiser/wideband digital receiver to target OEMs and aerospace & defence applications.
2015-05-22 Why Moore's Law is nowhere near ready to meet its maker
In 2003, Intel predicted an end to Moore's Law shortly after hitting the anticipated 16nm node, but today it seems we're on track for 10nm fairly soon with 7nm not far off.
2005-07-07 WEDC unveils new RISC MPU
The new WED3C755E8M-XBHX multi-chip package from White Electronic Designs features a 755 RISC processor (E die revision), dedicated 1MB SSRAM L2 cache, configured as 128K x 72 on a 21-by-25mm, 255 HBGA.
2014-11-03 Using interposers for DDR memory testing
So, say you need to get probes onto a dual data-rate memory device and some (or all) of the pins are inaccessible. Here is where chip interposers come in.
2012-05-25 UMC begins phase 5 & 6 of Fab 12A
The expansion begins UMC's new generation of 300mm manufacturing that will extend 28nm production and establish a solid foundation for 20nm and beyond to meet customers' high-end demand.
2013-10-11 TU Delft, Imec co-author test flow for 3D IC optimisation
3D-COSTAR aims to optimise the test flow of 3D stacked ICs by compiling the yields and costs of design, manufacturing packaging and logistics.
2016-03-21 TSMC unveils silicon plans
TSMC will enable silicon interposers larger than 1,200mm21.5x the reticle sizeat 7nm to enable giant 2.5-D stacks of logic and memory for the next gen of Cowos- chip on wafer on substrate.
2012-02-06 TSMC to roll 3D IC assembly service next year
The company has one year to get all physical design kits and EDA support in place to allow customers to design with COWOS, the technology standing for chip on wafer on substrate.
2015-09-21 TSMC heats up 10nm engine, preps 16nm for 2017
TSMC has gotten off to a slow start with its 16nm FinFET process and has also announced plans for specialty RRAM and MRAM memories that would act as alternatives to embedded flash.
2014-04-25 TSMC fleshes out IC line-up with shrunk TSVs
Based on its work on chip stacks, TSMC will launch in July an enhanced version of the 16nm FinFET technology with up to 18 per cent faster data rates and lower leakage, in addition to a planned 10mm and 7mm processes.
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