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2012-08-14 The significance of JESD204
The JESD204 offers several advantages over its CMOS and LVDS predecessors in terms of speed, size and cost.
2012-05-08 A primer on JESD204 standard for ADCs
Learn about this digital interface standard and its design implications.
2013-02-12 PHY performance metrics for JESD204B transmitter
There are several metrics to be evaluated when assessing the performance of the PHY for a JESD204B transmitter.
2008-06-16 Parallel makes a comeback
Before you know it, we're back to where we were years ago, with large banks of parallel paths, except now clocking at much higher speeds.
2013-12-30 Examining JESD204B converter protocol advances
JESD204 was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
2013-09-26 Xilinx, ADI achieve JEDEC JESD204B interoperability
The companies announced that they have achieved JESD204B interoperability between Xilinx JESD204 LogiCORE IP in the Kintex-7 FPGA and the ADI AD9250 analogue-to-digital high-speed data converter.
2013-07-04 Understanding the control characters in JESD204B
Here's a closer examination of the control characters that are employed in the JESD204 interface.
2008-09-16 Jedec spec standardizes 8B/10B gains
IBM Corp.'s 8B/10B makes single transmission-line-pair communications possible at frequencies above 2GHz. Jedec specification JESD204 defines the protocol and electrical characteristics required to standardize the implementation of this coded interface for data converters, enabling a new generation of faster and more accurate serial ADCs.
2012-11-29 Using JESD204B for wideband data converter apps
The JESD204A/B interface minimises the number of digital inputs/outputs between data converters and other devices, such as FPGAs and SoCs.
2012-04-18 Survival guide to high-speed ADC digital outputs
Learn about the key attributes of CMOS, LVDS, and CML outputs, and their performance tradeoffs.
2008-04-16 Serial-output ADC needs fewer FPGA I/O pins
The high-speed 2-wire serial interface of Linear Tech's LTC2274 ADC reduces the number of data I/O lines required between a 16bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single, self-clocking, differential pair communicating at 2.1Gbit/s.
2008-11-24 Multichannel ADCs save up to 50% PCB space
Analog Devices Inc. has released four-channel 12bit ADCs that use 50 percent less PCB surface.
2008-06-27 Lattice IP cores aim at wireless base stations
The folks at Lattice Semiconductor have announced the availability of three new intellectual property core and reference design products targeting the wireless communications market.
2012-07-10 Gigabit serial links paves way for multi-core scalability
Built on top of the serdes for data-intensive apps, gigabit serial interfaces minimize system cost and pin count while improving parallelism, performance and capacity.
2012-10-16 Advantages of JESD204B over parallel data formats
High-speed serial interfaces may still come with implementation issues, but the standardization reduces the adoption risk.
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