total search30 articles
| 2013-09-26 | Xilinx, ADI achieve JEDEC JESD204B interoperability The companies announced that they have achieved JESD204B interoperability between Xilinx JESD204 LogiCORE IP in the Kintex-7 FPGA and the ADI AD9250 analogue-to-digital high-speed data converter. |
| 2012-11-29 | Using JESD204B for wideband data converter apps The JESD204A/B interface minimises the number of digital inputs/outputs between data converters and other devices, such as FPGAs and SoCs. |
| 2013-07-04 | Understanding the control characters in JESD204B Here's a closer examination of the control characters that are employed in the JESD204 interface. |
| 2013-02-12 | PHY performance metrics for JESD204B transmitter There are several metrics to be evaluated when assessing the performance of the PHY for a JESD204B transmitter. |
| 2013-07-22 | PHY IP platform supports JESD204B, CPRI and OBSAI SBMULTR2T2812G SiIP PHY from Semtech is tuned to meet the performance of each standard through a programmable profile that sets a set of registers that control the operation of the PHY. |
| 2014-12-08 | JESD204B clock device targets LTE, GSM base stations The AD9528 from ADI offers a low-power, multi-output, clock distribution function with low-jitter performance, along with an on-chip, two-stage PLL and VCO, to tackle GSPS data converter applications. |
| 2014-08-21 | Exploring JESD204B interface This article discusses the evolution of the JEDEC JESD204B standard and its benefits, including faster data rates, simplified PCB layout, smaller package sizes, and lower cost. |
| 2013-12-30 | Examining JESD204B converter protocol advances JESD204 was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface. |
| 2014-12-10 | eASIC completes JESD204B interoperability at 10Gb/s Analog Devices' AD9234 12bit, 1GSPS high-speed dual ADC can interoperate with the eASIC Nextreme-3 28nm that eases the design and integration of high bandwidth multi-channel radios. |
| 2013-04-29 | Critical issues for functioning JESD204B interface Know the interface from an ADC to FPGA for JESD204B, how to identify when it is working right, and how to troubleshoot it if something is not quite right. |
| 2015-09-10 | Clock jitter attenuator boosts JESD204B serial interface The HMC7044 offers a wide range of clock management and distribution features that make it possible for designers of base stations to build an entire clock design with a single device. |
| 2013-05-31 | Channel compensation methods in JESD204B converter Converters with either the JESD204B receiver or transmitter can offer channel compensation strategies on their physical layer to minimise the design effort and time. |
| 2012-10-16 | Advantages of JESD204B over parallel data formats High-speed serial interfaces may still come with implementation issues, but the standardization reduces the adoption risk. |
| 2015-04-24 | TI bares FPGA alternative The 66AK2L06 programmable system-on-chip offers efficient, direct connection to analogue front end (AFE) using Texas Instrument's integrated KeyStone technology and JESD204B-compliant standards. |
| 2016-03-02 | Enhancing receiver sensitivity Several advances in ADC design such as the new JESD204B standard, coupled with the new low power amplifiers, ultimately improve system noise performance. |
| 2012-10-10 | Analog Devices rolls 14bit, 250MSPS ADC The dual-channel AD9250 touts the JEDEC JESD204B serial output data interface standard that accommodates the precise synchronisation of multiple data-conversion channels through a serial interface. |
| 2014-12-04 | Clock IC from ADI aimed at GSPS data converter apps The JESD204B-compatible AD9528 has an on-chip VCO that tunes from 3.6-4GHz, with the input receivers and oscillator providing both single-ended and differential operation. |
| 2015-12-22 | Top 10 innovative products of 2015 Many companies have introduced products in preparation for the growing IoT. There are also innovations in computing devices, where chips have not only become smaller but more powerful as well. |
| 2013-06-07 | TI rolls out KeyStone based SoC for PoE+, pico deployments TI's new TCI6630K2L SoC uses a dual ARM Cortex-A15 RISC processors and four of TI's fixed- and floating-point TMS320C66x digital signal processor (DSP) generation cores. |
| 2012-08-14 | The significance of JESD204 The JESD204 offers several advantages over its CMOS and LVDS predecessors in terms of speed, size and cost. |
| 2012-04-18 | Survival guide to high-speed ADC digital outputs Learn about the key attributes of CMOS, LVDS, and CML outputs, and their performance tradeoffs. |
| 2014-06-12 | RFSDK accelerates base band-to-radio configuration The RFSDK includes a complete integration framework to hook up the base band with integrated transceivers or digital front end with discrete data converters. |
| 2014-11-21 | NXP, Xilinx aim to cut wireless infrastructure CapEx, OpEx The companies teamed up to allow customers to quickly and easily combine Xilinx's latest crest factor reduction and digital pre-distortion SmartCORE IP with NXP's Gen9 LDMOS RF power amplifiers. |
| 2014-02-20 | Millimetre wave modem IP supports 60GHz-80GHz Using a common platform, the 1.6Gbit/s wave modem IP from Xilinx addresses low power small cell backhaul and high throughput wireless fronthaul applications. |
| 2015-12-29 | Maxim rolls out 16bit 5.9Gsps modulating RF DAC The MAX5869 is optimised for digital video broadcast and cable applications and meets spectral mask requirements for a broad set of communication standards. |
| 2014-04-10 | LTE small cell processors boast AKM's latest RF transceiver AKM's RF transceiver products claim to enable LTE small cell makers to offer mobile operators with industry-leading performance within the low power budgets they require. |
| 2015-10-05 | IDT debuts jitter attenuator, frequency synthesisers The 8V19N407 and 8V19N408 support up to 3GHz output, as well as 82fs of RMS phase noise, addressing the requirements of multi-carrier GSM radio transceivers as well as 40Gb and 100Gb Ethernet PHYs. |
| 2012-07-10 | Gigabit serial links paves way for multi-core scalability Built on top of the serdes for data-intensive apps, gigabit serial interfaces minimize system cost and pin count while improving parallelism, performance and capacity. |
| 2014-11-13 | ADI receiver can digitise IF frequencies from 70-450MHz The AD6676 is a single-chip wideband IF receiver subsystem that can be configured to achieve a noise figure of 13dB, IIP3=36dBM, noise spectral density (NSD) as low as -160dBFS/Hz. |
| 2012-05-08 | A primer on JESD204 standard for ADCs Learn about this digital interface standard and its design implications. |
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