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2009-05-22 Power consumption and management for LatticeECP3 devices
This application note provides information on power supply considerations and the power calculations that the Power Calculator tool provides. Also included are some guidelines to reduce power consumption.
2009-05-19 LatticeECP3 sysIO usage guide
This application note describes the sysIO standards available and how to implement them using Lattice's ispLEVER design software.
2009-05-22 LatticeECP3 sysDSP usage guide
This application note discusses how to access the features of the LatticeECP3 sysDSP (digital signal processing) slice described in the LatticeECP3 Family Data Sheet.
2009-05-12 LatticeECP3 sysCONFIG usage guide
Configuration is the process of loading or programming a design into volatile memory of an SRAM-based FPGA. To support multiple configuration options, the LatticeECP3 supports the Lattice sysCONFIG interface as well as the dedicated ispJTAG port.
2009-05-13 LatticeECP3 sysCLOCK PLL/DLL design and usage guide
This application note describes the clock resources available in the LatticeECP3 device architecture. Details are provided for primary clocks, secondary clocks and edge clocks as well as clock elements such as PLLs, DLLs, clock dividers and more.
2009-05-25 LatticeECP3 soft error detection (SED) usage guide
Soft errors occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit. This application note describes the hardware based soft error detect (SED) approach taken by Lattice Semiconductor for LatticeECP3 FPGAs.
2009-05-12 LatticeECP3 Serdes/PCS usage guide
The LatticeECP3 FPGA family combines FPGA fabric, I/Os and up to 16 channels of embedded Serdes with associated Physical Coding Sublayer (PCS) logic. The PCS logic can be configured to support numerous industry-standard, high-speed serial data transfer protocols.
2009-05-20 LatticeECP3 memory usage guide
This technical application note discusses memory usage for the LatticeECP3 family of FPGA devices. It is intended to be used by design engineers as a guide to integrating the Embedded Block RAM (EBR)- and PFU-based memories for this device family in ispLEVER.
2009-05-20 LatticeECP3 high-speed I/O interface
This application note describes how to use the capabilities of the LatticeECP3 devices to implement the high-speed generic DDR interface, and the DDR, DDR2 and DDR3 memory interfaces.
2009-05-27 LatticeECP3 hardware checklist
When designing complex hardware using the LatticeECP3 FPGA, designers must pay special attention to critical hardware configuration requirements. This application note steps through these critical hardware implementation items relative to the LatticeECP3 device.
2010-06-22 LatticeECP3 and LatticeECP2M high-speed backplane measurements
This technical note outlines two experiments that measure the serdes backplane transmission performance thresholds of the LatticeECP3 and LatticeECP2M devices.
2011-02-10 IP suites speed design with LatticeECP3 FPGAs
To ease the design of electronic systems using Lattice Semiconductor's LatticeECP3 FPGA, the company introduces IP suites for PCIe, Ethernet networking, DSP, video & display, and value.
2009-08-27 Mid-range FPGA packs higher DSP capacity
Lattice Semiconductor Corp. has begun sampling of LatticeECP3(TM)-150 FPGA, the highest-density device in its high-value, low-power ECP3 mid-range FPGA family.
2009-06-04 Electrical recommendations for Lattice Serdes
LatticeECP3, LatticeECP2/M and LatticeSC/M Serdes integrates high-speed, differential current mode logic (CML) input and output buffers. Off-chip signal interface design and characteristics are the focus of this application note.
2011-02-25 Development kit eases HD video camera design
Lattice Semiconductor's HDR-60 video camera development kit is a production-ready HD video camera development system based on the LatticeECP3 FPGA family.
2011-12-15 Software promises speedier FPGA design
The Lattice Diamond design software targets high volume, cost- and power-sensitive applications.
2013-01-23 Lattice upgrades FPGA design software
The company debuted the latest versions of Lattice Diamond and iCEcube2 design tools that claim to improve power calculations and design productivity.
2011-06-15 IP core supports HSR protocol
Lattice Semiconductor Corp. and Flexibilis Oy unveil the triple speed Flexibilis Ethernet Switch IP cores operating on Ethernet Layer 2 and can switch with Gigabit forwarding capacity per port.
2011-07-07 FPGAs, PCIe IP core pass PCIe 2.0 compliance
Lattice Semiconductor's FPGA and PCIe IP core passed the PCI-SIG PCIe v2.0 compliance and interoperability testing for 1- and 4-lane configurations.
2010-11-10 FPGA design software updated
Lattice Diamond 1.1 extends support to MachXO and MachXO2 product families
2010-07-07 Design software delivers low-power, low-cost FPGAs
The Lattice Diamond FPGA Version 1.0 design software provides as set of tools and a modern user interface to enable designers to more quickly target low power, cost sensitive FPGA applications.
2009-02-26 65nm FPGAs, clock ICs defy downturn
Seeking to grab share in a down market, Lattice has introduced its first 65nm FPGAs in the market and has expanded its family of differential clock distribution ICs. It also announced the availability of 15 new reference designs and a new development kit for its MachXO PLD family.
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