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2008-09-16 Mentor, Cadence hoist verification to a new stature
Mentor and Cadence have announced the release of the latest version of the open-source Open Verification Methodology.
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams
2008-12-11 Open-source solution enables reuse of VMM code
Mentor Graphics Corp. announced the availability of an open-source SystemVerilog solution for users adopting the Open Verification Methodology (OVM). The solution enables the easy and flexible reuse of legacy Verification Methodology Manual (VMM) code within an OVM environment.
2008-12-09 Open source SystemVerilog solution rolls
Cadence Design Systems has released an open source SystemVerilog solution to help users include Synopsys Inc.'s Verification Methodology Manual verification IP (VMM VIP).
2003-08-18 Memory overwhelms current verification techniques
Circuit simulation is unable to provide adequate functional verification coverage for memories
2008-06-18 HDMI verification tool is OVM-ready
eInfochips has launched a universal verification component designed to verify HDMI transmitters and receivers
2007-08-22 Cadence, Mentor team on SystemVerilog methodology
Cadence Design Systems Inc. and Mentor Graphics Corp. have partnered to standardize on a verification methodology based on the IEEE Std. 1800-2005 SystemVerilog standard
2008-01-11 Cadence, Mentor launch Open Verification Methodology
A result of their joint efforts to unify the SystemVerilog method, Cadence Design Systems Inc. and Mentor Graphics Corp. ahs launched the Open Verification Methodology (OVM).
2008-01-21 Open' is (not) just a four-letter word
There is presently a measure of "openness fatigue" permeating the industry, but that's because the term "open" has been far too often applied to products and organizations that are far from open in significant ways
2006-09-06 Website offers free open source C++ IC verification tools
Two engineers have launched a website with open-source tools that can help IC verification teams with C++ verification
2004-01-01 Verification platform for Jeda language rolls
Jeda Technologies released Jeda-X, a commercial product based on the Jeda hardware verification language
2003-06-05 TransEDA debuts property verification tool
TransEDA has announced a property and assertion capture and validation tool at the 2003 Design Automation Conference.
2002-10-18 Synopsys, OCP-IP codevelop SoC methodology
Synopsys Inc. and the Open Core Protocol International Partnership has announced the development of a SystemC modeling methodology for OCP-based SoCs
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs
2006-09-15 Synopsis announces verification IP for OCP interface
Synopsys said it developed verification IP for the OCP interface in response to customer demand for using its DesignWare Library and VCS Verification Library to verify systems and cores that utilize OCP
2014-11-11 Shifting to requirements-driven verification, test
Here is an evaluation of the pros, cons and potential obstacles to requirements-driven verification and test so you may decide if it is the next step in evolution
2006-10-16 Open-source tools ease C++ verification
Two engineers published a book on IC verification with C++ and launched a website with free open-source tools that can help IC verification teams
2003-11-13 New verification platform is based on Jeda language
New verification platform is based on Jeda language
2010-03-05 IPL Alliance launches iPDK open standard
The Interoperable PDK Libraries (IPL) Alliance has released the first open standard for interoperable process design kits (iPDKs
2005-04-18 IP reuse simplifies design, verification
An automated integration of IP using a platform-based strategy may help designers simplify chip design and verification
2006-09-18 Averant dives deep into formal verification
Averant took advantage of Design Automation Conference to roll out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification
2008-06-05 ARM, Renesas, Synopsys draft low-power verification methodology
Synopsys Inc., ARM and Renesas Technology have collaborated to define the industry's first methodology to address the rapidly increasing complexity of low power verification
2007-07-16 Verify designs with assertions
When adopting components of assertion-based verification (ABV) into standard production flows, teams run into several challenges. This article gives tips and tricks when dealing with ABV
2010-06-24 Tips on reducing debug efforts
Debug will get your attention one way or another. If you give it attention early in the development cycle, it will reduce the amount of time spent on debug later and in future designs.
2008-03-25 New Platform Express supports IP-XACT 1.4
Mentor Graphics has made available a new version of Platform Express with full support for the IP-XACT 1.4 IP databook specification, new mixed-level RTL and ESL design capabilities, and a new portable generator format.
2008-06-10 eInfochips launches IP tool for improved functionality
EInfochips Ltd launched what it claims as the first SystemVerilog verification IP that will enable designers to better use key SystemVerilog functionality while cutting verification cycle times for designs and serve as blocks needed for DUT for system-level verification
2012-10-10 Developing reset-aware OVM testbench
Learn about each verification component and the changes required in consideration of the reset conditions
2008-04-01 'Openness' fulfills SystemVerilog promise
Notes Stan Krolikoski of Cadence Design Systems: Open Verification Methodology is a truly open SystemVerilog class library and methodology package that can be used free of any restraints imposed by either Cadence or Mentor.
2006-01-02 SystemVerilog won't kill 'e' language
Backers of 'e,' which is nearing IEEE standardization, say that rumors of the language's death are exaggerated.
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