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2005-09-12 Vienna to host nano-imprint litho seminar
Photomask vendor Photronics has said it will host a seminar on nano-imprint lithography during the Micro- and Nanoengineering Conference in Vienna, Austria, on Sept. 21
2007-05-04 ST picks nano-imprint litho solution from Obducat
STMicroelectronics has placed an order for a nano-imprint lithography (NIL) R&D system from Obducat AB to be used in a post-silicon R&D unit for development purposes
2011-03-07 Nano-imprint litho makes headway in IC world
Nano-imprint lithography tool vendors have achieved good defect density levels for the technology's imprint-specific defectivity, claiming that many tool platforms have shipped in the past year.
2013-01-22 Molecular Imprints comes first in 450mm race
Molecular Imprints Inc. has recently disclosed that one of their machines are being used by an unnamed semiconductor company to support the development of 450mm diameter wafers.
2007-02-08 Litho tool imprints 30 wafers per hour
Obducat's Sindre nano-imprint litho tool, named after a legendary blacksmith dwarf of Nordic mythology, is able to imprint 30 200mm wafers per hour
2011-03-04 JSR, IBM launch self-assembly litho structure
Targeted at the sub-20nm half-pitch node, the new DSA technology enables phase separation, resulting in good profiles and more flexible use in both logic and memory applications
2010-09-22 Forecast: all leading-edge designs will require e-beam
D2S Inc. CEO Aki Fujimora discusses the role of electron beam lithography in the future of semiconductor manufacturing.
2015-02-10 Extending Moore's Law with 1.5nm metrology tool
Argonne National Laboratory teamed up with aBeam and LBNL to develop what they say is the finest metrology tool in the world, at 1.5nm to target advanced semiconductor nodes.
2015-07-21 Semicon West highlights 10 chip trends
During the recent Semicon West, executives from a number of chip companies discussed the ongoing developments on semiconductors technology
2009-03-06 Litho woes: R&D gap, downturn
It was a triple-whammy for lithographers at the SPIE Advanced Lithography conference as the industry continues to be plagued by an R&D gap, technology delays, and, of course, the lousy economy
2010-07-20 Uncertainty marks future of advanced lithography
Industry players present in Semicon West's session on advanced lithography sparked arguments on what the future holds as complexities and costs increase.
2009-07-09 Top 10 industry issues
Here are the top 10 looming issues that the semiconductor capital equipment industry is facing.
2015-03-25 Semicon manufacturing welcomes EUV lithography progress
The recent SPIE Advanced Lithography conference showcased a number of headway in extreme ultraviolet lithography that could possibly redefine how the process is being conducted.
2009-03-02 Panelists skeptical on next-gen litho
Experts debated and sparred over the future of patterning during a panel discussion at the SPIE Advanced Lithography conference.
2005-11-15 Nanoelectronics market growing, says SEMI
The markets for nano materials, tools and equipment for nanoelectronics totaled $1.8 billion in 2005 and is forecast to reach $4.2 billion by 2010, according to a market research report from SEMI.
2007-02-27 IBM pushes for immersion at 22nm
IBM outlined last week its lithography roadmap, saying that it would extend 193nm immersion lithography down to the 22nm node for logic production.
2007-08-13 Fujitsu claims HDD patterned media breakthrough
Fujitsu has claimed a breakthrough in patterned media HDD by achieving the basic read/write capability of ideally 'ordered' alumina nanoholes on a 2.5-inch magnetic disk with a flying head.
2008-11-17 Fab tech roll call: survival of the fittest
Manufacturers are rolling out 45nm ICs, with 32nm designs in the works; 22nm and even smaller devices are in R&D. But delivery of chips at 32nm and beyond won't be a cool breeze.
2011-03-07 Directed self-assembly gains steam
Despite its inherent defects, DSA could have applications in areas such as flash memory production where the regular structure of circuits and cost sensitivity of the market may make it attractive.
2014-05-08 3D chip-making technique utilises metallisation layers
The technique fabricates active devices interleaved between the metallisation layers atop a standard CMOS die, eliminating the expense of vertically stacked transistors or of stacking dies with TSVs.
2009-01-06 2009 IC fearless forecasts
2009 is just beginning to unfold in the electronics industry and there is already a looming uncertainty based on recent industry data.
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