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2008-06-02 Understand, test OCP SystemC channel models
The OCP Protocol is a high-performance and bus-independent interface protocol between intellectual property cores that provides a standard for Electronic System Level design. It improves IP core reusability, making more predictable and productive SoC designs.
2002-11-07 Tower Semiconductor supports OCP Partnership
Tower Semiconductor Ltd has taken part of the Open Core Protocol International Partnership.
2002-10-18 Synopsys, OCP-IP codevelop SoC methodology
Synopsys Inc. and the Open Core Protocol International Partnership has announced the development of a SystemC modeling methodology for OCP-based SoCs.
2006-09-15 Synopsis announces verification IP for OCP interface
Synopsys said it developed verification IP for the OCP interface in response to customer demand for using its DesignWare Library and VCS Verification Library to verify systems and cores that utilize OCP.
2009-11-12 Optimizing OCP slave memory behavior
Verification IP for open-core protocol (OCP) is generally used to achieve one of two main verification objectivesat the module level to test OCP components and their interfaces, or at the bus fabric level when some or all of the components may be replaced by the verification IP to test the behavior of a system.
2006-01-02 On-chip instrumentation aids OCP debugging
Debug analysis and on-chip instrumentation are evolving to support more complex chips, addressing issues such as bus-level debug.
2005-01-17 OCP-IP upgrades core to bus validation tool
The latest version of OCP-IP's front end OCP validation tool is fully compliant with, and supports the OCP 2.0 spec.
2007-03-08 OCP-IP launches network-on-chip benchmarking initiative
The Open Core Protocol International Partnership is launching a network-on-chip benchmarking initiative. The first deliverable is a new white paper that outlines the essential features of an NoC benchmarking environment.
2004-03-01 OCP modules operate at 2.7Gbps per channel
Optical Communication Products' nLIGHTEN 2300 modules provide high-density interconnect solution for short-reach data communication applications.
2002-07-31 OCP introduces extended transmission distance transceivers
Optical Communication Products Inc. has introduced its High Sensitivity CWDM Transceivers in GBIC format with an extended transmission distance of over 100km.
2003-02-04 OCP acquires Gore optical module assets
Optical Communication Products Inc. has acquired the parallel optical module assets and IP of Gore Photonics.
2002-10-14 OCP acquires business assets of Cielo Comm
Optical Communication Products Inc. has acquired certain assets of Cielo Communications.
2005-05-12 Mentor's CheckerWare verification IP supporting OCP interface
Open Core Protocol International Partnership (OCP-IP) said that the OCP interface has been added to Mentor Graphics Corp.'s CheckerWare library of verification intellectual property (IP).
2007-11-01 Improve embedded 3D graphics with OCP
Using the Open Core Protocol can reduce the time and cost of developing 3D graphics technology for the embedded space.
2008-09-01 Automate formal verification for OCP
The automation of formal protocol verification using VIPs enables a rapid and exhaustive verification of critical IP interfaces. Once a VIP library is written and tested, it can be re-used to improve the verification quality and shorten the verification schedule. VIPs can also be used to ease the verification of high-level system properties since they provide a "free" environment.
2007-01-24 Transceivers come in new operating temperature options
OCP said it is addressing the expanded application requirements of the XFP market by offering additional operating temperature options to its optical transceiver portfolio.
2003-10-17 MIPS unveils new line of synthesizable cores
MIPS Technologies Inc. has unveiled four members of its 32-bit synthesizable core family that are derivatives of the MIPS32 24K microarchitecture.
2006-10-04 Yogitech unveils 'first' Open Core Protocol UVC
Yogitech, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol universal verification component.
2016-03-15 Vicor's 48V modules support Google's 48V server infrastructure
The modules allow for more efficient, dense, cost-effective and reliable power distribution, meeting what Google aims to promote as server and distribution infrastructure standard for data centers.
2005-01-27 Via prepares to raise processor clock frequency to 2GHz
Via Technologies is preparing to improve the performance of its CPU family to achieve a 2GHz clock frequency this year, which would help allay some user complaints that its low-power benefits don't completely make up for its lack of horsepower.
2012-06-19 Use U8030 power supply output sequencing feature
Read about three test applications that demonstrate the capabilities of the U8030 Series power supply.
2009-12-17 USB 3.0 controller achieves over 430MBps throughput
Evatronix SA has launched the SuperSpeed USB 3.0 device controller that is claimed to reach over 430MBps of throughput.
2009-05-04 USB 2.0 OVP device packs high-speed ESD protection
ON Semiconductor has developed the NCP362, claimed to be the industry's first overvoltage protection (OVP) device with both integrated current protection and high-speed ESD protection for USB 2.0 applications in portable, telecom, consumer and computing systems.
2007-08-06 Tiny switching regulators promise high efficiency
Allegro MicroSystems Inc. has introduced a family of high efficiency switching regulators for portable and office automation apps, which promises to deliver high operating frequencies.
2007-11-09 Tensilica unwraps 'smallest' 32bit processor core
Tensilica Inc. says it has released the industry's smallest licensable 32bit processor core based on an industry-standard architecture.
2006-04-03 SystemC assertions go 'native'
Jeda Technologies shelved its own Jeda verification language in favor of a new tool suite supposedly equipped with the industry's first 'native' SystemC assertion-based verification automation capability.
2005-09-30 Synopsys testbench solution increases verification productivity
Synopsys announced Discovery Pioneer-NTB, a new SystemVerilog testbench automation tool that claims to increase verification productivity and improve the quality of complex SoC and IP designs.
2006-05-01 Summit Design offers 'personal edition' of SystemC IDE on Web
The Vista-PE, touting all the features of the full-fledged Vista IDE at the module level, hopes to help people bring up and explore SystemC.
2014-11-26 Start-up eyes parallel CPU with 10x leap in performance
A start-up founded by two teenagers is designing a parallel processor that it hopes delivers a 10x leap in performance per watt for high-end systems. Rex Computing will make open source its instruction set architecture in hopes of rallying supporters around it.
2006-06-29 ST unrolls controller for resonant half-bridge topology
STMicroelectronics introduced an advanced double-ended controller specifically designed for the series-resonant half-bridge topology.
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