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2007-08-23 Synopsys left out in SystemVerilog OVM initiative
Synopsys was not invited to join the OVM initiative recently announced by Cadence Design Systems and Mentor Graphics.
2008-06-18 HDMI verification tool is OVM-ready
eInfochips has launched a universal verification component designed to verify HDMI transmitters and receivers.
2012-10-10 Developing reset-aware OVM testbench
Learn about each verification component and the changes required in consideration of the reset conditions.
2009-05-22 Debugging stimulus generation in VMM, OVM testbenches
This article reviews the components of stimulus generation in the VMM and OVM environments, and outlines a typical layered stimulus solution. It also takes a look at the different capabilities available for debugging
2010-03-31 Configuring the testbench using OVM configuration classes
This technical paper is a testimony to the fact that configuration classes, when used properly, greatly improve the configurability and adaptability of a verification environment.
2008-02-19 Cadence, Mentor enhance OVM source-code library
Cadence Design Systems and Mentor Graphics have announced an enhanced release of the source-code library and user documentation for the Open Verification Methodology (OVM), claimed to be the industry's first open, interoperable SystemVerilog verification methodology.
2008-09-16 Mentor, Cadence hoist verification to a new stature
Mentor and Cadence have announced the release of the latest version of the open-source Open Verification Methodology.
2007-10-16 Cadence, Mentor unify SystemVerilog method
Cadence Design Systems Inc. and Mentor Graphics Corp. have joined forces to promote a common approach to the verification of design files based on SystemVerilog.
2008-01-11 Cadence, Mentor launch Open Verification Methodology
A result of their joint efforts to unify the SystemVerilog method, Cadence Design Systems Inc. and Mentor Graphics Corp. ahs launched the Open Verification Methodology (OVM).
2012-01-03 Protocol transactors tout faster SoC verification
The Veloce transactors enable the use of stimuli generated by modern simulation test benches including SystemVerilog/OVM and UVM, SystemC and C-based environments
2008-12-11 Open-source solution enables reuse of VMM code
Mentor Graphics Corp. announced the availability of an open-source SystemVerilog solution for users adopting the Open Verification Methodology (OVM). The solution enables the easy and flexible reuse of legacy Verification Methodology Manual (VMM) code within an OVM environment.
2007-08-29 Verification kit supports advanced techniques
Cadence Design Systems' new verification kit for SoC designs that aims to enable engineers to adopt advanced verification techniques with reduced risk and deployment effort.
2008-03-25 The real deal on Synopsys' Synplicity buyout
Synopsys has signed a definitive agreement to acquire Synplicity for $8 cash per share, resulting in a gross transaction of approximately $227 million, and approximately $188 million net of cash acquired. Here's what EDA veteran Gabe Moretti thinks about the deal.
2016-05-16 The ideal union of PAM and Ethernet
Understand how various Ethernet speeds evolved through the utilisation of various pulse amplitude modulation (PAM) schemes.
2011-02-09 Synopsis launches verification migration program
Synopsys has launched its verification FastForward migration program and invited Cadence Incisive and Mentor Questa users to join.
2012-08-30 Overcoming challenges for SoC verification team
Know the unique problems that SoC verification engineers face and the approach that provides them a level of automation similar to that enjoyed by block-level verification teams.
2008-12-09 Open source SystemVerilog solution rolls
Cadence Design Systems has released an open source SystemVerilog solution to help users include Synopsys Inc.'s Verification Methodology Manual verification IP (VMM VIP).
2008-03-25 New Platform Express supports IP-XACT 1.4
Mentor Graphics has made available a new version of Platform Express with full support for the IP-XACT 1.4 IP databook specification, new mixed-level RTL and ESL design capabilities, and a new portable generator format.
2012-10-30 KALRAY completes 256-core SoC using Mentor's sol'ns
The KALRAY MPPA-256 manycore processor is a 256-core SoC with 47MB memory using Mentor's functional verification, physical design and verification, and design-for-test flow product suites.
2005-02-18 Intel, partners put their trust in Bulverde for secure mobile transactions
Intel Corp. has been shipping to selected customers a version of its Bulverde XScale-based applications processor for mobile devices that includes a hardware security block based on Trusted Computing Modules,
2008-09-30 Intel, Chartered criticize chip IP industry
The semiconductor intellectual property (IP) industry has been the virtual and ongoing punching bag in the IC business.
2007-08-22 Cadence, Mentor team on SystemVerilog methodology
Cadence Design Systems Inc. and Mentor Graphics Corp. have partnered to standardize on a verification methodology based on the IEEE Std. 1800-2005 SystemVerilog standard.
2008-11-28 Cadence downplays Connections membership issue
A Cadence Design Systems Inc. executive downplayed a report that first surfaced on EDA tool users' site Deepchip.com, which said that the company had "evicted" from membership a large number of software vendors from its Connections partnership program.
2008-04-01 'Openness' fulfills SystemVerilog promise
Notes Stan Krolikoski of Cadence Design Systems: Open Verification Methodology is a truly open SystemVerilog class library and methodology package that can be used free of any restraints imposed by either Cadence or Mentor.
2008-01-21 'Open' is (not) just a four-letter word
There is presently a measure of "openness fatigue" permeating the industry, but that's because the term "open" has been far too often applied to products and organizations that are far from open in significant ways.
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