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| 2007-11-30 | ST favors Mentor's place and route system STMicroelectronics has taped out an advanced process, multimillion-gate STB chip using the Mentor Graphics Corp.'s Olympus-SoC place and route system. |
| 2012-10-30 | KALRAY completes 256-core SoC using Mentor's sol'ns The KALRAY MPPA-256 manycore processor is a 256-core SoC with 47MB memory using Mentor's functional verification, physical design and verification, and design-for-test flow product suites. |
| 2006-08-04 | IC implementation device targets 65nm/45nm designs Sierra Design Automation said its Olympus-SoC is targeted for high-end customers who are designing at 65nm and below processes. |
| 2007-12-17 | SI solution provides multimode/corner capability for 65/45nm Mentor Graphics has released a new technology in its Olympus-SoC place and route product that accelerates SI closure and improves the reliability of manufactured silicon. |
| 2007-05-30 | Routing suite receives 45nm design update Gearing up to deal with 45nm IC physical design challenges such as interconnect resistance, Sierra Design Automation Inc. this week is announcing three significant enhancements to its Olympus-SoC placement and routing suite. |
| 2010-10-25 | Place and route system increases design variability Nvidia Corp. has licensed the Olympus SoC place and route system of Mentor Graphics for its high performance graphics processors. |
| 2008-10-16 | Parallel tech simplifies system analysis, task execution Mentor Graphics Corp. has launched a new task-oriented parallelism technology in the company's Olympus-SoC place-and-route system that provides timing analysis and optimization tasks to run in parallel. |
| 2013-06-03 | Mentor Graphics, Globalfoundries team up for 20nm kits Mentor Graphics and Globalfoundries recently unveiled a collaboration to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform. |
| 2012-10-17 | TSMC names EDA partners for CoWoS, 20nm TSMC has validated technologies from Cadence, Mentor and ANSYS for use in its 20nm and CoWoS design infrastructure. |
| 2013-06-04 | TSMC certifies Mentor EDA tools for 16nm FinFET Mentor Graphics design and verification tools get certified for TSMC's 16nm FinFET process node. The companies also detailed their continued collaboration on 20nm physical verification kit optimisations. |
| 2007-06-14 | Rivals play down threat of Mentor's Sierra acquisition Mentor Graphics' rivals—Synopsys, Cadence and Magma Design—regard Mentor's Sierra acquisition as a minimal threat, and their own positions in 65/45nm IC design as strong. |
| 2007-07-16 | Multicore reshapes EDA landscape The largest EDA vendors acknowledge that the advent of multicore processors is a cause for both celebration and concern. Multicore platforms will provide much-needed compute power as transistor counts soar at 65nm and below. But legacy applications could prove difficult or even impossible to parallelize. |
| 2014-09-30 | Mentor Graphics, TSMC team up for 10nm FinFET designs The collaboration targets 10nm FinFET process requirements for early customers' test chip and IP design starts through the use of physical design, analysis, verification and optimisation tools. |
| 2007-06-13 | Mentor acquires Sierra Design for $90M Mentor Graphics has acquired Sierra Design Automation, a provider of high-performance place and route solutions, for $90 million. |
| 2012-06-20 | Handling behemoth designs Learn about some strategies and tool requirements for physical implementation of large and complex semiconductors. |
| 2009-10-21 | GlobalFoundries taps Mentor EDA tools GlobalFoundries chose Mentor Graphics for its physical verification, RET, OPC and mask data preparation solutions. |
| 2008-08-26 | Despite Q2 loss, Mentor remains positive Mentor Graphics Corp. made a loss of $17.2 million on revenue of $182.4 million in Q2 ended July 31. |
| 2015-04-08 | ACM announces IC physical design contest winners The annual International Symposium on Physical Design (ISPD) showcases innovations in modern IC design, and this year also saw Kurt Antreich being awarded for his achievements in EDA. |
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