Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Advanced Search > PCI 3.0

PCI 3.0 Search results

?
?
total search128 articles
2005-03-28 First PCI 3.0-compliant UART
Exar's XR17V258 UART devices will support 66MHz PCI bus interfacesup to 8 channels with 32bit data
2006-08-28 Exar unrolls 'first' quad-channel 66MHz PCI 3.0 compliant UART
Exar has announced a quad-channel 66MHz PCI 3.0 compliant UART device, said to be the industry's first such product.
2009-03-12 USB 3.0 wins Gennum support
The USB's drive into Gbit territory got another backer when Gennum Corp. announced an integrated PHY and controller for USB 3.0 available for licensing as a silicon block
2009-02-16 USB 3.0 Speedsnow and later
The performance of any standard is based not on just the standard, but the implementation. It's always execution that matters.
2006-02-14 UART/PCI controller tackles high density serial connectivity
Combining eight high performance UARTs and a PCI compliant host interface in a single chip, Oxford Semiconductor's new communications controller provides designers with the means to dramatically simplify multi-port serial to PCI bus design
2012-03-19 Test sol'ns ease integration of PCIe 3.0 in Intel Xeon processors
Tektronix products that support development of the processors include DPO/DSA/MSO70000 series oscilloscopes, TLA7SA16/TLA7SA08 logic protocol analyzer modules and TLA7000 series logic analyzers.
2013-05-24 Stratix V GX FPGAs added to PCI-SIG integrators list
Altera's Stratix V GX FPGAs successfully passed all PCI-SIG compliance and interoperability tests, completing inclusion for Stratix V on all three generations of the Integrators Lists for PCIe
2013-01-08 ST introduces DOCSIS 3.0 cable-modem ICs
The DOCSIS 3.0 modem SoCs provide up to 16 downlink channels, with four uplink channels, enabling data speeds of up to 800Mb/s downstream and 108Mb/s upstream
2008-05-26 Powering and configuring Spartan-3 Generation FPGAs in compliant PCI applications
The information presented in this application note applies to compliant PCI applications using Spartan-3 Generation FPGAs
2010-11-23 PCIe Spec 3.0 doubles interconnect bandwidth
Products designed to the PCIe 3.0 architecture can achieve bandwidth near 1GBps in one direction on a single-lane configuration and scale to an aggregate approaching 32GBps on sixteen-lanes
2009-07-20 PCIe 3.0 gears for 8GHz by next year
PCI Special Interest Group has announced that the final specification for PCIe 3.0 will be released by June 2010.
2007-08-14 PCIe 3.0 draft spec triggers debate
A debate on some of the technical decisions behind the draft specification for PCIe 3.0 has surfaced within hours of the announcement of the first details of the draft spec
2009-06-10 PCIe 3.0 cores support up to 16 lanes
Gennum Corp.'s Snowbush IP group has completed silicon core designs of a controller and PHY device for PCIe version 3.0
2010-06-25 PCIe 3.0 compliance testing pushed back to 2011
The PCI SIG released interim 0.71 version of the PCIe 3.0 that supports up to 8GTps and aims to start testing for compliance in early 2011, about a year later than originally anticipated.
2011-02-14 PCI/104-Express SBC embeds for rugged apps
Advanced Digital Logic's ADLD25PC single board computer is designed for applications in harsh environments including transportation, military and aerospace.
2008-01-16 PCI-SIG brews PCIe ver 2.0 enhancements
The PCI Special Interest Group is making progress on a basket of feature extensions to its latest 2.0 specification, all of which should be available by June at the latest
2007-08-10 PCI SIG sets PCIe 3.0 at 8GTps
Putting a stop to the long debate on the bit rate for the next-generation PCIe, the PCI SIG has finally set 8GTps as the bit rate for the 3.0 version.
2012-09-17 PCI Express to be in tablets and smartphones
PCI-SIG will be approving software that will enable PCI Express to become mobile-friendly
2004-08-17 Nvidia rolls out latest PCI-based graphics solution
Nvidia introduced a new family of professional graphics products that is based on the PCI Express bus architecture
2012-10-15 Module from Kontron extends lifecycle of PCI/ISA-based apps
The Kontron ETX module with AMD Embedded G-Series APU T16R claims to add an upgrade path for Geode-based ETX designs and low-power systems.
2006-08-21 Kontron unveils compact baseboard for ETX 3.0
Kontron America is readying its ETX miniBaseboard, an extremely compact Embedded Technology eXtended (ETX) baseboard.
2012-04-24 Kontron COM Express modules for PCI based designs
With support for Direct X 11 and OpenGL 4.0, the Computer-on-Modules COMe-cOH2 claim to offer the latest graphics features and bring a new user experience to SFF gaming and Kiosk POI/POS systems.
2011-12-26 Graphics market integrates 28nm tech, PCI Express 3.0
The Radeon HD 7970 integrates new graphics core next architecture that enables new levels of gaming and computing capabilities.
2014-08-06 Flash-backed DRAM rides PCIe 3.0 bus
The Flashtec card from PCM claims to offer better performance than flash-based SSD without its endurance issues, delivering 10 million IOPS when used as additional system memory.
2011-03-03 DesignWare IP supports PCIe 3.0 specification
Synopsis Inc. has added enhancements to its DesignWare digital controllers to support PCI Express 3.0 specification.
2008-09-12 Custom PCI timing budgets for Spartan-3 Generation FPGAs
The PCI Local Bus Specification, Revision 3.0 (the PCI specification), defines two timing budgets. One timing budget is for use with 33MHz operation, and the other timing budget is for use with 66MHz operation. These two timing budgets define the I/O timing parameters for compliant 33MHz and 66MHz components.
2008-05-26 Custom PCI timing budgets for Spartan-3 generation FPGAs
The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices. The provided example applies this information to a design using Xilinx Spartan-3 Generation FPGAs with Xilinx LogiCORE PCI interfaces
2012-03-08 Comply with receiver test based on PCIe 3.0 CEM specification
Read about RX test, which is used to determine the receiver's capability to properly detect the digital signal content, even for worst-case impaired input signals.
2011-07-01 China ramps USB 3.0 interconnect production
With the growing trend for faster data transmission in storage devices, connector and cable assembly makers in China are upping their production of USB 3.0 interconnects
2009-08-05 AMD, HP seek PCIe 3.0 extensions
Advanced Micro Devices and Hewlett-Packard researchers have written two extensions to the PCIe 3.0 specification, which aim to enable lower cost chips that could support multiple protocols and reduce processor overhead
Bloggers Say

Bloggers Say

See what engineers like you are posting on our pages.

?
?
Back to Top