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2003-02-12 PGA adapter withstands >1.5kV overload voltage
Shenzhen Nuoling Electronic Co. Ltd's board-to-board type PGA adapter is rated at 60V, 3A and can withstand an overload voltage >1.5kV.
2002-08-28 Molex PGA socket suits mobile Pentium 4, Celeron
The Micro PGA socket is designed to be used with Intel's Mobile Pentium 4 and Mobile Celeron processors for applications such as blade servers or thin notebook PCs.
2003-04-10 Microchip PGA provides digital control of analog domain
Microchip Technology's MCP62Sx programmable gain amplifier enables user to have digital control of the analog domain with the integration of an amplifier, mux, and gain control selected via a SPI bus.
2002-10-10 Linear Tech PGA offers gain of 100
Linear Tech's LTC6910-1 PGA features inverting gains from 0 to 100 that are digitally-selectable using a 3-bit control input.
2002-07-29 Corex ZIF PGA socket offers 20-milliohm contact resistance
The 1318 series of ZIF PGA sockets have 478 contacts made of gold-plated phosphor bronze with a pitch of 1.27mm and contact resistance of 20 milliohms.
2005-05-31 Athlon dual-core processor fits in 939-pin micro PGA packaging
AMD says its new Athlon 64 X2 dual-core processor delivers the performance of a multi-core processor with the same 939-pin micro PGA type packaging as the single-core Athlon 64 CPU.
2003-06-03 AIC PGA connector enables fewer board layer tests
The surface-mount, interstitial PGA connector from AIC involves the application of the patented BGA socket adapter system in an existing, molded PGA wafer.
2013-01-23 24bit ADCs offer on-chip, ultra-low noise PGA
Intersil Corporation's ISL26102 and ISL2610424bit ADCs gain range facilitates direct connection to load cells, thermocouples and other popular sensors with a wide variety of sensitivities.
2000-06-27 Xilinx FPGAs: A technical overview for the first-time user
This application note introduces the reader to the various Xilinx product families' logic components and provides a general overview of what the logic components within the devices are used for.
2000-06-26 XC4000 series technical information
This application note contains additional information that may be of use when designing with XC4000 Series devices. This information supplements the product descriptions and specifications, and is provided for guidance only.
2000-06-21 XC4000 series edge-triggered and dual-port RAM capability
This application note examines the edge-triggered capability of the XC4000 FPGAs to simplify system timing and provide better performance for RAM-based designs. It also discusses these FPGAs' dual-port mode, which offers new capabilities and simplifies FIFO designs.
2000-06-28 XC3000 series technical information
This application note contains additional information that may be of use when designing with the XC3000 series of FPGA devices. This information supplements the data sheets, and is provided for guidance only.
2000-06-23 Virtex synthesizable high-performance SDRAM controller
This application note describes the design and implementation of a synthesizable, parameterizable, flexible, auto-placed-and-routed synchronous DRAM controller in the Virtex FPGA family.
2000-06-21 Virtex power estimator user guide
This application note explains how to use the Power Estimator worksheet, which is used to calculate estimated power consumption for Virtex designs. This worksheet considers the design resource usage, toggle rates, I/O power, and many other factors in the estimation.
2000-06-21 Using three-state enable registers in XLA, XV, and SpartanXL FPGAs
This application note shows how to use hard macros to implement the use of the internal IOB three-state control register, which can significantly improve output enable and disable time, in both HDL- and schematic-based designs.
2000-06-23 Using the XC4000 readback capability
This application note describes the XC4000 readback capability and its use. It discusses initialization of the readback feature, format of the configuration and readback bit streams, timing considerations, software support for reading back LCA devices, and CRC.
2000-06-21 Using the Virtex SelectIO
This application note describes how to utilize the highly configurable, high-performance SelectIO I/O resources of the Virtex FPGA series to provide support for a wide variety of I/O standards.
2000-06-26 Using the Virtex delay-locked loop
This application note demonstrates how to use the Virtex FPGA Series' four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits to implement several circuits that improve and simplify system-level design.
2000-06-23 Using the Virtex Block SelectRAM+
This application note demonstrates how to utilize the Virtex FPGA Series' dedicated blocks of on-chip 4.096kb dual-port synchronous RAM by using each port of the block SelectRAM+ memory independently as a read/write, read or write port, and configure each port to a specific data width.
2000-06-22 Using the dedicated carry logic in XC4000E
This application note describes the operation of the XC4000E dedicated carry logic, the standard configurations provided for its use, and how these are combined into arithmetic functions and counters.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2000-06-21 Using Select-RAM Memory in XC4000 Series FPGAs
This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning.
2000-06-22 Using programmable logic to accelerate DSP functions
This application note implements a programmable logic solution for the computationally intensive functions found in DSP in order to provide increased DSP system performance at reduced system cost.
2000-06-21 Using manual power down mode with SpartanXL FPGAs
This application note provides all the information the designer needs to use the SpartanXL FPGAs' Power Down mode feature effectively, such as descriptions of the mode's common applications, internal functioning and electrical characteristics.
2000-06-22 Ultra-fast synchronous counters
This application note discusses the implementation of a fully synchronous, non-loadable, binary counter by using the XC4000 and XC3000 FPGA designs.
2000-07-01 Trends in multi-chip package integration
Wafer level packaging (WLP) technologies have recently attracted much development activity, innovation and investment. Here are some of the opportunities and obstacles for WLP and multi-chip package integration approaches.
2000-06-21 The low-cost, efficient serial configuration of Spartan FPGAs
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approach recommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size, and board space associated with the serial configuration circuitry.
2000-06-21 The express configuration of SpartanXL FPGAs
This application note provides information on how to perform Express configuration, which uses an 8-bit-wide bus path for fast configuration, specifically for the SpartanXL family of FPGAs.
2000-06-26 System design with new XC4000X I/O features
This application note examines the I/O features of the XC4000X FPGA family including an additional latch on each input and an output multiplexer on each output. These features are discussed, and examples show how to use them.
2000-06-23 Synthesizable 143MHz ZBT SRAM interface
This application note demonstrates a Virtex design that interfaces to megabytes of external high-speed ZBT (Zero Bus Turnaround) SRAM in order to provide interleaved read/write without wasteful turnaround cycles.
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