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2009-10-01 Virage expands interface IP solutions for CE
Virage Logic Corp. has added new interface IP products to join its SiPro product line, the group of products that have sprung from the company's January licensing agreement with Advanced Micro Devices Inc
2008-02-12 USB IP saves power, simplifies connection
Synopsys has expanded it DesignWare USB IP product line with support for the USB 2.0 Link Power Management and High Speed Inter-Chip standards
2008-12-18 USB 2.0 PHY on 40nmWhat's the big deal
The challenge is to build a circuit that can support 5V using a transistor, in the case of 40 nm, that has been only been rated to 1.8 V.
2003-06-03 UMC, Artisan co-develop PCI-Express PHY core
Semiconductor foundry UMC and Artisan Components Inc. have agreed upon a long-term IP collaboration focused on the development of a PCI-Express PHY IP core for UMC's 0.13?m chip designs.
2005-03-02 UMC 0.13?m HS process developed JMicron Serial ATA II PHY core
United Microelectronics Corp. (UMC) and JMicron Technology Corp. revealed that JMicron's Serial ATA (SATA) II PHY Technology has been developed and proven on UMC's 0.13?m HS (high speed) process
2015-09-28 The lowdown on MIPI D'PHY RX
MIPI D'Phy, a physical serial communicating layer connecting the application processor to the display device or the camera, offers advantages as the physical layer. Learn more about it
2012-11-30 Tensilica, mimoOn to offer LTE, LTE-A PHY IP sol'n
Through the agreement, Tensilica is now the exclusive DSP IP vendor for mimoOn's LTE user equipment and eNodeB (base station) PHY software products.
2007-07-05 Synopsys, UMC partner on 65/90nm connectivity IP
Synopsys announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCIe, serial ATA and XAUI PHY semiconductor IP to UMC's 90nm and 65nm technologies.
2010-08-06 Synopsys, GlobalFoundries collaborate on 28nm Designware PHY IP
Synopsys Inc. and GlobalFoundries Inc. have agreed to collaborate on the development of a DesignWare interface PHY IP for use on a 28nm process.
2005-05-12 Synopsys' PCI Express IP solution achieves PCI-SIG compliance
Synopsys Inc. said that its DesignWare physical layer (PHY) and digital controller intellectual property (IP) have achieved compliance with the PCI Express standard from the PCI-Special Interest Group (PCI-SIG).
2013-09-24 Synopsys uses TSMC's 20nm SoC process for interface IP
The silicon-proven Synopsys DesignWare USB, DDR, PCI Express and MIPI PHY IP on TSMC's 20nm SoC process is designed to achieve high yield by meeting the requirements of advanced manufacturing design.
2006-09-07 Synopsys unrolls connectivity IP for SMIC 130nm tech
Synopsys has expanded its DesignWare MSIP portfolio with the release of connectivity IP for SMIC's 130nm technology
2008-04-22 Synopsys touts first certified USB 2.0 PHY IP for 45nm
Synopsys Inc. has announced that its DesignWare USB 2.0 nanoPHY is the first 45nm USB 2.0 PHY IP to successfully pass the USB Implementers Forum Hi-Speed USB PHY certification.
2015-09-23 Synopsys rolls out IP line for TSMC 10nm FinFET process
The company said this milestone allows designers to speed the development of SoCs that incorporate USB 3.1, USB 3.0, USB 2.0, HSIC, PCI Express 3.0, PCI Express 2.0 and MIPI D-PHY interface IP.
2005-05-17 Synopsys IP achieves USB OTG certification
Synopsys Inc.'s DesignWare universal serial bus on-the-go (USB OTG) digital core and three physical interfaces (PHYs) have been certified by the USB Implementers Forum.
2006-02-13 Synopsys extends DesignWare USB 2.0 PHY lineup
Synopsys announced the addition of the new DesignWare USB 2.0 nanoPHY intellectual property to its existing DesignWare USB 2.0 physical layer product line.
2015-07-31 Synopsys DesignWare IP now compliant on TSMC's 16FF+ process
Synopsys Inc. achieved compliance for a range of DesignWare IP on the TSMC 16nm FinFET Plus process including USB 2.0 and USB 3.0, PCI Express 3.1, HDMI 2.0, MIPI D-PHYSM and SATA IP solutions
2015-04-09 Synopsys debuts PHY IPs for TSMC's 16nm FinFET Plus process
The DesignWare PHY IP portfolio enables designers to integrate required functionality in mobile and enterprise SoCs with less risk, while accelerating the development of SoCs.
2014-05-23 Synopsys adapts IP solution for PCI Express 4.0
The DesignWare IP supporting the PCIe 4.0 architectureincluding controller, verification, and PHYlowers integration risk and accelerates availability of devices integrating the 16GT/s speed.
2005-09-27 ST, Synopsys demonstrate SATA IP compatibility for 90nm
STMicroelectronics and Synopsys announced that they are working together to conduct Serial ATA (SATA) interoperability testing using ST's 90nm Multi-Interface PHY (MIPHY) physical layer interface macro-cell and Synopsys' DesignWare SATA host controller intellectual property (IP) core.
2008-08-21 ST showcases first PHY IP for 6Gbit/s SATA HDDs
STMicroelectronics has demonstrated the world's first MIPHY PHY interface for the new 6Gbit/s SATA technology
2007-05-31 Serial ATA PHY core suits low-power designs
Mentor Graphics Corp.'s new SATA PHY IP core, which is targeted for the TSMC 130nm LVOD process, provides a completely integrated solution for both SATA host and device applications running at up to 3Gbps.
2014-06-12 Semtech reveals HMC-compliant PHY IP
The Snowbush 28nm platform physical layer IP has met the interoperability requirements of the Hybrid Memory Cube standard with significant margin and passed the testing required by Micron
2009-02-25 Plug and Play IP goal remains "elusive" or is becoming tangible
DesignCon's IP Selection panel essentially painted the view that plug and play IP remains 'elusive.' Here is my view that this goal is becoming tangible
2010-02-01 PHY IP solution eases HDMI 1.4 integration
Synopsys Inc. has launched the high-quality DesignWare HDMI 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification.
2013-07-22 PHY IP platform supports JESD204B, CPRI and OBSAI
SBMULTR2T2812G SiIP PHY from Semtech is tuned to meet the performance of each standard through a programmable profile that sets a set of registers that control the operation of the PHY
2008-05-02 PHY IP handles 5Gbit/s PCIe 2.0 PHY IP
Synopsys has rolled the DesignWare PHY IP for PCIe 2.0 (Gen II), based on the PCIe 2.0 base specification.
2012-02-17 PHY IP enables fast HDMI integration
The DesignWare HDMI 1.4 IP solution is fully compliant with both HDMI and high-bandwidth digital content protection specifications and has received certification from HDMI authorized testing centers
2015-06-24 PCIe IP with system-level data protection targets cloud apps
The DesignWare Controller IP for PCIe 4.0 supports multiple lanes/datapath widths for optimal configurations, as well as Native, ARM AMBA AXI-3 and AMBA AXI-4 interfaces for easy integration into SoCs
2012-03-05 MIPI digital controller IP cuts mobile phone cost
Arteris FlexLLI offers point-to-point interconnect between two chips such as a mobile phone application processor and modem baseband processor, reducing compatibility risk.
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