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What are PLDs?
PLDs or programmable logic devices refer to a variety of logic chips that are programmable at the user's site. Programmability of logic means that new chip designs can be tested and easily changed without incurring the huge photomask costs for chips completed in a fab. In addition, memory-based PLDs can be reprogrammed over and over, which allows working products to be upgraded at the user's site.
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2003-01-22 Lattice pushes low-power PLDs into handhelds
The company has come up with a zero-power programmable logic architecture that consumes less than 40?A in standby.
2002-07-16 Lattice lands programmable-logic combo punch
Lattice Semiconductor has announced a new architecture that combines the programming attributes of CPLDs and FPGAs.
2002-11-08 Lattice ispLSI5000VA, aspMACH4A3, and MAX7000B Performance Comparison
This application note compares three popular CPLD architectures: the ispLSI5000VA, ispMACH4A3 and MAX7000B.
2001-04-04 Latches and flip-flops with PLS153
This application note discusses the use of the logic functions of the PLS153 PLD in implementing memory functions, such as latches and edge-triggered flip-flops, with a relatively small part of the chip and without external wiring.
2002-04-17 Last leg of IIC-China series successfully held in Shenzhen
The Shenzhen leg of the 7th annual International IC ? China Conference and Exhibition, which is co-located with the 2nd Embedded Systems Conferences ? China, was successfully staged April 15 and 16 at the China Hi-Tech Exhibition Center.
2005-04-08 Largest member of CPLD family
The EPM2210 device, the largest member of Altera's MAX II complex PLD family that features 2,210 logic elements, is now shipping in volume.
2007-03-12 J drive: In-system programming of IEEE standard 1532 devices
The J Drive programming engine provides immediate and direct in-system configuration support for IEEE Standard 1532 PLDs. To configure an in-system device, the programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language file to apply configuration data from the 1532 data file through the IEEE Standard 1149.1 test access port.
2001-03-21 ISR programming using an embedded processor with Jam
This application note illustrates how to use the Jam Programming and Test Language to program ISR PLDs using an embedded processor.
2002-10-11 ispLSI 8000V Family VHDL Code Examples
This application note talks about the ispLSI8000V family architecture features and includes coding examples designed to allow the user to take advantage of its hardware capabilities.
2002-12-06 ispLSI 5384VE application: High speed binary counter
This application note discusses how to implement a high-speed binary counter using the ispLSI 5384VE CPLD.
2002-12-06 ispLever starter kit
This application note describes the uses and the contents of the ispLEVER starter kit for ISP CPLDs.
2002-12-06 ISP Introduction
This application note provides an introduction on In-system programming and JTAG.
2002-03-01 IP security key to design success
This news article focuses on the importance of IP security in engineering designs as ASICs can now be easily implemented in FPGAs.
2012-02-23 Intel to make Tabula's 22nm devices
For years, Intel only dabbled in ASIC and foundry sector. Since the Achronix deal was announced, some analysts saw that the chip giant was set to increase its presence it the foundry space dominated by TSMC.
2002-03-01 Integration trends in programmable logic
This news article illustrates the integration issues of programmable logic devices with other system functionality to drive PLDs in ASIC applications.
2005-11-01 Integrate flash device programming, reduce cost
Flash memory devices offer high density and low cost to engineers who seek devices that are easy to program and erase.
2005-01-17 Inside a hybrid verification model
The combination of languages, tools, IP and methodologies has morphed the traditional ASIC design cycle into a 'hybrid model' process. Learn more.
2000-06-26 In-system programming times for XC9500XL
This application note discusses the in-system programming speed of the XC9500XL devices.
2002-12-06 Implementing an SDRAM controller in a Lattice ispLSI device
This application note discusses how to implement an SDRAM controller using an ispLSI CPLD.
2001-03-28 Implementing a synchronous DRAM controller in Cypress CPLDs
This application note discusses the implementation of an SDRAM controller for a Pentium processor by using Cypress Semiconductor's CPLD.
2001-03-21 Implementing a 128Kx32 dual-port RAM using the FLASH370
This application note describes how to implement a 128K-by-32-bit-wide dual-port memory or larger, using high-speed 1MB SRAMs and Cypress Semiconductor's CY7C371 CPLD.
2000-03-20 Implementing 66MHz-64bit PCI with an FPGA
This paper illustrates how to use the SX-A FPGAs to implement the CorePCI 66MHz-64bit Target+DMA design, a high performance design that currently cannot be realized with any other FPGA architecture.
2006-08-16 Implement broadcast video infrastructure
PLDs will play an increasingly important role in the digital buildup of the broadcast industry infrastructure.
2002-03-01 How FPGAs are simplifying board designs
This brief news article describes how the programmable logic industry, despite the current economic downturn, remains one of the fastest growing segments of the semiconductor business.
2000-06-26 hongkong@xilinx.com
This application note provides a framework for planning high-speed XC9500XL CPLD designs by addressing certain issues, such as noise, ground bounce, signal coupling, ringing and reflections capacitance, early in the design process.
2001-04-04 High-speed 8-bit parallel-to-serial converter
This application note discusses how to implement a high-speed 8-bit parallel-to-serial data converter.
2001-04-01 Hardware implementations of multi-rate digital filters
It is important to efficiently map interpolation and decimation functions into hardware. Here is a look at DSP, PLD, and ASIC implementations for multi-rate filters.
2002-03-01 FPSoC: The next-gen FPGA design
This news article describes the necessary tools required to support the next generation of FPGAs called Field Programmable System-on-Chips.
2008-09-01 FPGAs qualify for cars, low-power apps
With the entire semiconductor industry in a state of flux and established markets offering little growth, programmable logic (PL) suppliers are exploring new opportunities. One of the promising markets that FPGA and CPLD vendors have been looking into is the automotive sector.
2008-08-01 FPGAs are all set for next process nodes
Altera Corp. today is expected to become the first FPGA vendor to launch a family of 40nm FPGAs. In addition, Altera will announce the 40nm HardCopy IV structured ASICs, as well as corresponding software tools for both device types. The families promise to enable a new class of single-chip, multicore and related complex devices.
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