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What are PLDs?

PLDs or programmable logic devices refer to a variety of logic chips that are programmable at the user's site. Programmability of logic means that new chip designs can be tested and easily changed without incurring the huge photomask costs for chips completed in a fab. In addition, memory-based PLDs can be reprogrammed over and over, which allows working products to be upgraded at the user's site.

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2003-02-17	FPGA on-chip debug with off-chip benefits This article will address some of the limitations of on-chip debug and show users an alternative that combines the best of both worlds--on-chip debug with off-chip, deep sample storage.
2006-08-30	FPGA addresses low-power requirements of mobile market Actel rolled out a new family of FPGAs that is touted to be the industry's lowest-power FPGAs in the market.
2001-03-19	FLASH370i 5V to 12V dc-dc converter solutions This application note provides various solutions for the 12V super-voltage requirement for Cypress Semiconductor's Flash-based In-System Reprogrammable CPLDs in designs that do not already include a source for 12V.
2001-03-21	FIFO Dipstick using Warp2 VHDL and the CY7C371 This application note presents a method by which FIFOs of any size may be monitored by an external PLD that will then generate all of the flags necessary for most FIFO applications.
2002-12-06	Fast Ethernet convergence sublayer This application note discusses the Fast Ethernet's convergence sublayer in a Lattice CPLD.
2005-03-21	Fabless firms outpace IDMs in costs, gross margins Fabless chip makers in the "core silicon space" are enjoying lower costs and much higher gross margins than their integrated device manufacturing (IDM) counterparts, according to a report from iSuppli Corp.
2005-01-06	Emerging $5-FPGA, a mainstream market Today, as the economy and new markets are forcing designers to look for solutions with ever-lower prices, the emergence of the $5 FPGA is becoming a mainstream market.
2002-04-08	Embedded processors for programmable logic This article describes soft processor cores for PLDs as well as the process of embedding high-performance hard macro processors into PLDs.
2001-03-21	Efficient arithmetic designs with Cypress CPLDs This application note is intended to provide designers with some insight into efficient means of implementing arithmetic functions in Cypress Semiconductor's CPLDs.
1999-11-24	EDA software support The ACCESS program provides a total solution that allows designers to generate and verify multiple design revisions that reduces product development cycle. This application note identifies the type of products available in each ACCESS partner, i.e., design entry, compilation, synthesis, and simulation.
2002-06-12	Downturn crimps ASIC design starts The ASIC industry has taken an unusually hard battering in the latest semiconductor industry downturn, with the number of design starts dropping along with revenue, according to analysts from Gartner Dataquest.
2000-06-29	Designing with XC9500XL CPLDs This application note describes design considerations of using the Xilinx XC9500XL CPLD.
2001-03-19	Designing with the CY7C335 and Warp2 VHDL compiler This application note provides an overview of the CY7C335 Universal Synchronous EPLD architecture and Warp2 VHDL Compiler for PLDs.
2001-03-23	Designing with Cypress in-system reprogrammable (ISR) CPLDs for PC cable programming This application note presents how to design with the Cypress In-System Reprogrammable (ISR) families of CPLDs, which includes the FLASH370i family and the Ultra37000 family, for programming from a PC with the ISR programming cable.
2002-10-01	Design Trends and EDA Tools: China & Taiwan This joint study by EE Times鏈卻ia and Gartner Dataquest conducted in the year 2002 reveals information on the latest design trends in China and Taiwan. The white paper is the result of a survey conducted by EE Times鏈卻ia on China- and Taiwan-based electronics design community across industries.
2003-09-18	Design Trends and EDA Tools: China & Taiwan This joint study by EE Times鏈卻ia and Gartner Dataquest conducted in the year 2003 reveals information on the latest design trends in China and Taiwan. The white paper is the result of a survey conducted by EE Times鏈卻ia on China- and Taiwan-based electronics design community across industries.
2005-10-03	Design Trends and EDA Tools: China & Taiwan IC and PCB design engineers in China and Taiwan reveal the current level of design and share development experience with EDA tools
2002-03-13	Design Trends & EDA Tools: China As China extends its electronic design capabilities, its market for EDA software is expected to demonstrate the region's highest growth potential with a CAGR of 30% during the five-year period ending 2005. This joint study by EE Times鏈卻ia and Gartner Dataquest reveals information on the latest design trends in China. The white paper is the result of a survey conducted by EE Times鏈卻ia on China-based electronics design community across industries.
2001-03-30	Design optimization using Warp synthesis directives This application note introduces synthesis directives and shows the tradeoffs that can be made to gain the best possible densities and speeds for VHDL or schematic implementations. It discusses various Warp synthesis directives, their formats and the purpose of each directive.
2000-03-17	Design of an MP3 portable player using a CoolRunner CPLD This application note describes the design specs of the MP3 portable player using a CoolRunner CPLD.
2000-06-26	Design of 4Mb Virtual SPROM This application note describes the design of a very low cost, CPLD-based virtual SPROM for downloading programming information to the Xilinx high-density XC4000 Series FPGAs.
2001-03-21	Delta39K PLL and clock tree This application note provides information and instruction in utilizing the functionality of the Delta39K PLL and associated clock tree.
2001-03-21	Delta39K and Quantum38K dual-port RAM This application note provides information and instruction in implementing synchronous/asynchronous dual-port RAM (DPRAM) in Delta39K and Quantum38K CPLDs.
2004-04-30	Dangerous cycle may be ahead, Altera CEO warns John Daane, President and CEO of Altera, reflects the snapshot of the semiconductor industry's first quarter and the preview of the coming year for PL.
1999-06-29	Customizable multi-channel HDLC controller with PCI interface in CPLD This paper describes a CPLD-based approach that fulfills the higher performance requirements while offering a degree of customization unavailable with off-shelf products.
2002-03-01	CPLDs encroach on FPGA territory This news article describes how with the programmable logic market experiencing tremendous growth, designers should position themselves to implement integrated, design-specific logic functions using standard components.
2001-03-19	CPLD power consumption comparison This application note presents a power consumption comparison among the 5V and 3.3V CPLDs that are being offered by Altera, Cypress, Lattice, Vantis and Xilinx.
2000-09-05	CPLD design hints for Atmel-Synario This application note provides hints for new or experienced users on how to use Atmel-Synario to efficiently implement their designs into Atmel PLD and CPLD devices.
2001-03-19	Converting designs from FLASH370i to Ultra37000 devices This application note addresses the issues associated with upgrading a design from a FLASH370 or a FLASH370i CPLD to an Ultra37000 CPLD.
2000-09-27	Content-addressable memory (CAM) and its network applications For any application that requires a fast memory search, CAM can provide a solution. There are many manufacturers that provide discrete CAM components and this paper discusses the importance of selecting the right company to properly address this technology.