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What is PLL?
A phase-locked loop or phase lock loop (PLL) is a control system which generates a signal that has a fixed relation to the phase of a "reference" signal. A PLL circuit responds to both the frequency and the phase of the input signals, automatically raisin
total search199 articles
2005-02-18 Web downloadable design tool suite supports new LatticeEC FPGAs
Lattice announced the immediate availability of v4.2 of its web-downloadable ispLEVER-Starter programmable logic design tool suite.
2005-06-13 VIA integrates Sandwork debugging tools into IC design flow
The analog and mixed-signal debugging tools from Sandwork Design Inc. have been incorporated into the IC design flow of Taiwan-based VIA Technologies Inc.
2015-04-27 Verilog-AMS vs SPICE view for SoC verification
In this article, we comparatively analyse the usage of Verilog/Verilog-AMS and SPICE views from the perspective of data converters and clocking IPs in an SoC.
2015-02-12 Verilog-AMS vs SPICE view for power management
Verilog-AMS is a behavioural abstraction of the circuit that sacrifices accuracy for the sake of run time, while SPICE does exactly the opposite. Here's a comparative analysis from a power management perspective.
2006-11-22 Vectron touts 'smallest' frequency translator
Vectron International said it has released the industry's smallest quartz-based, ultralow-jitter frequency translator.
2004-02-02 Vectorless test: Best bet for high-speed I/O
An approach called vectorless test is emerging that offers the best of both approaches: the cost effectiveness of on-chip I/O BIST combined with ATE-based signal integrity measurements.
2014-05-05 VadaTech kits out MCH with 40GbE option, advanced clocking
The MCH boasts up to four times boost in performance and enables highly flexible master/slave clock and time synchronisation to multiple clocking standards, leading to precision timing, aligned frequency/phase of the signals, and risk elimination involving packet loss due to buffer overflow.
2011-07-25 Understanding power issues in SDI products (Part 1)
Learn about the considerations to make when designing with analog and mixed-signal serial digital interface components.
2003-07-02 UMC, Spirea to produce WLAN radio chips
United Microelectronics Corp. has delivered Spirea AB's TripleTraC and gTraC WLAN radios using its 0.18?m RF CMOS process.
2006-10-11 UMC, Actel partner on 'lowest' power FPGA
Actel and UMC have teamed up to produce Actel IGLOO family, touted as the industry's 'lowest' power FPGAs.
2007-04-25 TSMC's IP moves stir up concern among providers
TSMC's move to broaden its portfolios of internally developed semiconductor IP and third-party IP has some observers asking whether the company is migrating to a more ASIC-like business model.
2006-12-08 True Circuits rolls out silicon proven 65nm analog IP
True Circuits Inc. has announced "silicon proven" phase-locked loop and delay-locked loop hard macros using TSMC's 65nm process.
2002-09-16 Toshiba, Neolinear formulate new methodology for Soc design
Toshiba and Neolinear teams up to implement a new AMS design methodology that enables significant analog design reuse.
2003-09-22 Toshiba licenses Barcelona analog synthesis solutions
Toshiba Corp. has licensed Barcelona Design Inc.'s analog synthesis solutions for use on its 0.13?m and 90nm processes.
2004-08-19 TI IC includes three PLL filter components
Touted by TI to offer a best-in-class performance, the company's latest clocking IC features three on-chip phase locked loop filter components.
2005-10-25 TI clock multiplier integrates three on-chip PLL components
TI announced that they have developed a clock multiplier that integrates three on-chip phase locked loop components to provide "industry-leading" flexibility and performance.
2007-07-16 TI clock generators offer low jitter performance
TI has introduced a family of highly programmable, one-to-four PLL clock generators that deliver very low jitter at 60ps typical for consumer applications.
2013-12-23 The lowdown on high-perf timing in board design
Know the various scenarios facing board designers when working with high-performance timing.
2009-01-29 The bad stuff impacting DDR timing budgets and ways to avoid 'em
Why bother with a DDR "PHY" when some SSTL I/O's with potentially a DLL or PLL slapped together with glue logic will do the trick of interfacing to an SDRAM?
2009-10-23 Techniques for evaluating deterministic jitter
This article discusses the effects of power supply noise interference on PLL-based clock generators and describes measurement techniques for evaluating the resulting deterministic jitter.
2012-03-21 Taking advantage of MCU sleep modes to boost energy savings
Learn about the different MCU modes that allow energy conservation.
2006-01-26 Synthesis tool combines advantages of flat, hierarchical design
It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra tackles the latter challenge with its Pinnacle Chip Assembly solution.
2004-05-24 Synopsys releases design platform upgrade
Synopsys launched an upgrade to its design platform that delivers across-the-board improvements in run-time, capacity, QoR, silicon technology support and turn-around time.
2012-12-07 Synchroniser with programmable MTBF capabilities
Here's a high frequency synchroniser circuit with programmable mean-time-between-failure capabilities well suited for high frequency clock gating and input signal synchronisation applications.
2013-07-08 SyncE timing chips boast phase jitter below 300fs RMS
The IDT 82V3910 and 82V3911 are low-jitter, highly-versatile SyncE network timing solutions optimised for use in 10GBASE-R/10GBASE-W and 40GBASE-R applications.
2005-11-11 Structured ASIC devices embed PCI Express physical layer
ChipX has introduced a new structured ASIC family that it claims is a low-risk alternative to traditional ASIC and FPGA devices
2003-02-26 STMicro expands 8-bit Flash MCU line
The company has expanded its ST7Lite series of 8-bit Flash MCUs with the introduction of the ST7FLite1 and ST7FLite2 units.
2006-10-16 Startups take on analog design automation
Automating analog IC design has proven to be a tough challenge, but two EDA startups are promising to do just that with a new "analog synthesis" technology.
2007-11-01 Spread spectrum confronts EMI
The sleepy clock-generator chip market shook itself awake as two rival vendors, Cypress Semiconductor and SpectraLinear rolled entries in a new class of programmable devices.
2006-09-21 Spice circuit simulator speeds time-to-results
Magma Design Automation has released a circuit simulator that dramatically speeds time-to-results for simulation and analysis while maintaining the accuracy of leading Spice simulators.
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