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What is PLL?
A phase-locked loop or phase lock loop (PLL) is a control system which generates a signal that has a fixed relation to the phase of a "reference" signal. A PLL circuit responds to both the frequency and the phase of the input signals, automatically raisin
total search199 articles
2009-12-23 Implementing PLL reconfiguration in Stratix III devices
This application note describes the flow for implementing PLL reconfiguration in Stratix III devices.
2013-02-26 Implement analogue functions in rugged FPGAs
By using digital implementations of analogue functions, engineers can add critical functionality without adding weight, power or size to the design.
2005-05-31 IDT unveils new PC clock devices for Intel platforms
Integrated Device Technology announced the availability of new PC clock devices that support Intel's next-generation notebook and desktop PC platforms
2004-06-02 IDT launches PC clock devices for next-gen desktop PCs
IDT unveiled a new family of PC clock devices targeting next-generation desktop PC platforms for the performance and mainstream markets.
2011-08-03 IC sales to peak in 3Q12
Semiconductor sales will grow slowly and steadily until 3Q12 before revenues start to drop, says The Information Network.
2002-03-05 IBM will steer PowerPC into mobile mart
IBM intends to take its PowerPC processor architecture to the mobile sector and into "head-to-head competition with Intel" and that company's Xscale processor, John Kelly III, senior vice president of IBM's Technology Group, said last week.
2004-12-15 IBM researchers discover servo control method for optics
IBM Corp. researchers from the company's server division and Thomas J. Watson Research Center have collaborated on an unusual project to bring the advantages of phase-locked loops to wavelength domains.
2005-09-08 How to interface DDR-II SRAMs with Stratix II devices
DDR-II SRAM devices offer enhanced timing margin and flexibility
2014-10-16 How to improve FPGA comms interface clock jitters
Know how external phase locked loops can be used to resolve problems faced when dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes.
2009-01-13 HardCopy II ASIC fitting techniques
This application note describes some possible design considerations and solutions for fitting a Stratix II FPGA design into a HardCopy II ASIC.
2007-03-08 GbE line-card IC offers synchronization at the PHY
Zarlink's single-chip GbE line card chip has been demonstrated to enable synchronization over the Ethernet PHY.
2002-12-19 Fujitsu rolls PLL synthesizers for WLAN designs
Fujitsu Microelectronics America has released the MB15F76UL and MB15F74UL HF dual serial input PLL synthesizers for wireless LAN systems.
2007-04-19 FME, Toric reveal results of embedded jitter project
Fujitsu Microelectronics Europe and Toric disclosed the results of their collaboration to verify embedded jitter-suppressing macros based on Toric's patented Anti-Jitter Cell technology.
2013-03-12 Epson's VCXO tweaked for LTE base stations, optical comms
Epson has touted its VG-4513CB as the industry's first VCXO to deliver output frequencies up to 500MHz without using a PLL or frequency multiplier
2003-09-01 Embedded Linux technologies: More power to you
While users perceive results of power management in terms of battery life, it is really a combination of CPU capabilities, system software, middleware and policy.
2003-05-21 Dini Group offers Stratix FPGA development platform
Altera Corporation and Dini Group has released the DN5000k10 platform that is based on Altera's Stratix FPGAs and is said to be ideal for algorithm acceleration, logic emulation, and reconfigurable computing applications.
2009-07-28 Digi-Key, Fujitsu ink distribution deal
Digi-Key has signed a new agreement with Fujitsu Microelectronics America for the worldwide distribution of the latter's new low-power, low-pin-count, 8bit MCUs and digital touchscreen sensor ICs.
2014-11-12 Determine acceptable jitter level in embedded design
Learn about the nuances of clock jitter specifications, and know how to determine the acceptable level of jitter early on in the development cycle to prevent dire impact on end product release schedules.
2012-02-29 Designing high frequency synchronizer with programmable MTBF features
Read about a high frequency synchronizer circuit with programmable mean-time-between-failure capabilities that is well suited for high frequency clock gating and input signal synchronization applications.
2013-11-04 Design the appropriate high-speed ATE hardware
Designing ATE hardware should not be taken lightly as a simple error could cost you another four to six weeks on your schedule.
2007-05-01 Design a single-chip, six-band UMTS transceiver for global connectivity
Find out what you need to design a truly global phone with full wireless connectivity.
2008-08-08 DDR regulator fits low-power memory termination
TI has launched a sink/source DDR termination regulator that is suited for all power management requirements for DDR, DDR2, DDR3 and DDR4 low-power memory termination.
2008-08-18 DDR IP solutions speed up SoC design operation
Synopsys has introduced a full range of silicon- proven DesignWare DDR IP solutions for SoCs that need an interface to high-performance DDR3, DDR2 and DDR memory subsystems.
2006-06-06 Dallas Semi rolls out timing-card-on-a-chip solution
Dallas Semi's DS3100 is touted to be the industry's only "timing-card-on-a-chip" solution for SONET/SDH synchronization.
2007-08-16 Create high-quality program for at-speed test
At-speed test has been improved by a number of new capabilities, including the use of on-chip-generated functional clocks during test mode. This article offers some do's and don'ts for creating a high-quality program for at-speed test.
2006-09-20 CPRI Serdes delivers 800ps delay calibration accuracy
National said its new CPRI Serdes is the first to guarantee 800ps delay calibration measurement accuracy and exceed all CPRI interface signal voltage and jitter requirements.
2006-11-16 Consider a structured-ASIC design methodology
Rob Schreck enumerates the do's and don'ts for using a structured-ASIC design methodology.
2004-01-26 Configurable logic device merges ASIC, FPGA features
The industry's quest for the best of both ASIC and FPGA worlds' s with Leopard Logic's Gladiator configurable logic device (CLD).
2006-03-16 CMOS op amp tailored for industrial, telecom apps
The new, rail-to-rail output CMOS op amp from National Semiconductor offers a wide operating range up to 24V and meets requirements of industrial and telecommunications applications.
2008-04-08 CMOS harmonic oscillator eliminates quartz crystals
Mobius Microsystems Inc. has unveiled its CMOS Harmonic Oscillator (CHO) technology that eliminates the need for quartz crystals in many applications. By integrating an oscillator onto an ordinary CMOS chip, the company claims to have removed the last moving part from electronics circuitry.
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