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2005-12-16 Where are the tools for next node?
If you're an EDA tool provider, it would be hard to find a more demanding customer than STMicro's Philippe Magarshack.
2004-12-13 STMicro keynoter sings praises of transaction level modeling
Philippe Magarshack, group vice president of central R&D at STMicroelectronics, made the 20km journey down the mountain from Crolles to provide a keynote presentation to the IP-SOC 2004 conference, which opened here today.
2009-02-03 Synopsys, ST team up on SI sign-off tools
Synopsys Inc. and STMicroelectronics have agreed to join forces to accelerate the development of methodologies and flows for low-power and high-performance SoC timing sign-off to reliably unleash the full performance potential of advanced technology nodes.
2005-03-17 Synopsys unveils 'next-gen' compiler for physical design
Synopsys unveiled a physical design solution, which the company claims provides leading-edge performance and already carries endorsements by key IC suppliers.
2005-04-18 Synopsys unveils 'next-gen' compiler
The company introduces a physical design solution which it says provides concurrent clock tree synthesis, routing and yield optimization.
2011-06-07 STMicroelectronics completes 20nm chip tapeout
The tapeout of STMicroelectronics' first 20nm technology demonstrator test chip has been successfully completed with Synopsys.
2005-06-15 STMicro bares major breakthrough in SoC design
STMicroelectronics has revealed the publication of a book on chip design methodology.
2008-12-22 ST, Synopsys collaborate on 32nm components
Synopsys Inc. and STMicroelectronics NV have joined efforts to enable the readiness of key components in a 32nm design flow, including ST's standard cell library for low-power and high-performance design, and the support of the latest route rules in Synopsys' IC Compiler Zroute technology.
2013-11-08 ST, Memoir Systems combine memory, process tech
When integrated into products made using ST's FD-SOI, Memoir's Algorithmic Memories claim to deliver uncompromised performance as a result of FD-SOI's recognised power and performance advantages.
2013-07-31 ST, ARM and Cadence team up for tool, model interoperability
The collaboration of ST, ARM and Cadence aims to increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level.
2006-05-29 ST certifies Mentor Catapult C Synthesis Libraries
Mentor Graphics announced that STMicroelectronics has added Catapult C Synthesis libraries to its standard ASIC design kit.
2007-02-15 ST adopts Synopsys compiler for ASIC design
STMicroelectronics has deployed Synopsys Inc.'s Design Compiler topographical technology in its 90nm and 65nm ASIC design flow to eliminate design iterations and streamline the overall design cycle for its internal design groups and external customers.
2005-07-19 Speakers eye design-manufacturing link
Viable system-on-chip (SoC) business models require an integration of design and manufacturing, along with new types of businesses and alliances, according to several speakers at the Multi-Processor SoC (MPSoC) forum.
2005-06-01 OEMs to EDA world: Time to catch up
If the EDA industry provides tools on time, it will continue to be a growing market, says Dataquest analyst.
2010-03-18 Mentor, ST co-develop 32/20nm design solutions
Mentor Graphics Corp. and STMicroelectronics have entered a broad-scoped collaboration to develop advanced design solutions at the 32nm technology node and down to 20nm node.
2011-02-16 ISSCS 2011 takes peek at new Imec tech
Among the results to be presented are a biomedical signal processor, a reconfigurable transceiver that eliminates the need for SAW filters and a functional 8bit MCU made by organic thin-film transistors.
2007-11-08 IBM-led alliance ups investment in 32nm packaging
The Common Platform alliance led by IBM plans to increase its investment in semiconductor packaging technology to pave the way to 32nm devices.
2010-05-14 ESD physical integrity tool enables early prototyping
The PathFinder ESD integrity solution aims to enable designers to perform early prototyping, circuit optimization and full-chip signoff.
2005-09-12 Cadence takes on OpenAccess 2.2 across all electronic designs
Cadence Design Systems Inc. has adopted the industry-standard OpenAccess 2.2 as a unified database for its IC implementation platforms and DFM solutions.
2002-05-16 Avant! partners with STMicro in IC, package design
Avant! Corp. has entered into a strategic technology alliance with STMicroelectronics to develop and deploy concurrent IC and package design and analysis capability.
2009-02-23 Apache, ST to address 45nm, 32nm issues
Apache Design Solutions Inc. and STMicroelectronics have expanded their business relationship and technical collaboration to address the upcoming power and noise challenges associated with 45nm and 32nm designs.
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