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2013-07-10 Hypres commercially debuts new chip fabrication process
The six-layer planarized chip fabrication process increases the integration level of superconducting ICs and critical current density of Josephson junctions.
2002-10-18 AmberWave cuts SiGe layer from strained-silicon process
AmberWave Systems Corp. claims to have worked out a form of strained silicon that removes the SiGe layer and provides an ultrathin silicon top layer to build high-performance devices.
2004-07-02 Palomar wire bonder with 300-by-150mm positioner
Palomar Technologies released its Model 8000 gold ball-and-stitch thermosonic wire bonder for complex, precision gold wire bonding apps.
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